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W9751G8KB 16 m ? ? publication release date: feb. 15, 2012 - 1 - revision a01 table of contents - 1. general description ................................ ................................ ................................ ................... 4 2. features ................................ ................................ ................................ ................................ ........... 4 3. key parameters ................................ ................................ ................................ ............................. 5 4. ball configuration ................................ ................................ ................................ ...................... 6 5. ball description ................................ ................................ ................................ ............................ 7 6. block diagram ................................ ................................ ................................ ................................ 8 7. functional de scription ................................ ................................ ................................ .............. 9 7.1 power - up and initialization sequence ................................ ................................ ................................ ... 9 7.2 mode register and extended mode registers operation ................................ ................................ ... 10 7.2.1 mode register set command (mrs) ................................ ................................ ............... 10 7.2.2 extend mode register set commands (emrs) ................................ .............................. 11 7.2.2.1 extend mode register set command (1), emr (1) ................................ ................ 11 7.2.2.2 dll enable/disable ................................ ................................ ................................ 12 7.2.2.3 extend mode register set command (2), emr (2) ................................ ................ 13 7.2.2.4 extend mode register set command (3), em r (3) ................................ ................ 14 7.2.3 off - chip driver (ocd) impedance adjustment ................................ ................................ 15 7.2.3.1 extended mode register for ocd impedance adjustment ................................ .... 16 7.2.3.2 ocd impedance adjust ................................ ................................ .......................... 16 7.2.3.3 drive mode ................................ ................................ ................................ ............. 17 7.2.4 on - die termination (odt) ................................ ................................ ............................... 18 7. 2.5 odt related timings ................................ ................................ ................................ ......... 18 7.2.5.1 mrs command to odt update delay ................................ ................................ ..... 18 7.3 command function ................................ ................................ ................................ ............................. 20 7.3.1 bank activate command ................................ ................................ ................................ .. 20 7.3.2 read command ................................ ................................ ................................ ............... 20 7.3.3 write command ................................ ................................ ................................ ............... 21 7.3.4 burst read with auto - precharge command ................................ ................................ ..... 21 7.3.5 burst write with auto - precharge command ................................ ................................ ..... 21 7.3.6 precharge all command ................................ ................................ ................................ .. 21 7.3.7 self refresh entry command ................................ ................................ .......................... 21 7.3.8 self refresh exit command ................................ ................................ ............................. 2 2 7.3.9 refresh command ................................ ................................ ................................ ........... 22 7.3.10 no - operation command ................................ ................................ ................................ .. 23 7.3. 11 device deselect command ................................ ................................ .............................. 23 7.4 read and write access modes ................................ ................................ ................................ ........... 23 7.4.1 posted ................................ ................................ ................................ .................... 23 7.4.1.1 examples of posted operation ................................ ................................ ..... 23 7.4.2 burst mode operation ................................ ................................ ................................ ....... 24 7.4.3 burst read mode operation ................................ ................................ ............................... 25 7.4.4 burst write mode operation ................................ ................................ .............................. 25 7.4.5 write data mask ................................ ................................ ................................ ............... 26 7.5 burst interrupt ................................ ................................ ................................ ................................ ..... 26 7.6 precharge operation ................................ ................................ ................................ ............................ 27 cas
W9751G8KB publication release date: feb. 15, 2012 - 2 - revision a01 7.6.1 bu rst read operation followed by precharge ................................ ................................ ..... 27 7.6.2 burst write operation followed by precharge ................................ ................................ .... 27 7.7 auto - precharge operation ................................ ................................ ................................ ................... 27 7.7.1 burst read with auto - precharge ................................ ................................ ....................... 28 7.7.2 burst write with auto - precharge ................................ ................................ ....................... 28 7.8 refresh operation ................................ ................................ ................................ ............................... 29 7.9 power down mode ................................ ................................ ................................ .............................. 29 7.9.1 power down entry ................................ ................................ ................................ ........... 30 7.9.2 power down exit ................................ ................................ ................................ .............. 30 7.10 input clock frequency change during precharge power down ................................ ............................. 30 8. operation mode ................................ ................................ ................................ ........................... 31 8.1 command truth table ................................ ................................ ................................ ........................ 31 8.2 cloc k enable (cke) truth table for synchronous transitions ................................ ........................... 32 8.3 data mask (dm) truth table ................................ ................................ ................................ ............... 32 8.4 function truth table ................................ ................................ ................................ ........................... 33 8.5 simplified stated diagram ................................ ................................ ................................ ................... 36 9. electrical characteristics ................................ ................................ ................................ ... 37 9.1 absolute maximum ratings ................................ ................................ ................................ ................ 37 9.2 operating temperature condition ................................ ................................ ................................ ....... 37 9.3 recommended dc operating conditions ................................ ................................ ........................... 37 9.4 odt dc electrical characteristics ................................ ................................ ................................ ...... 38 9.5 input dc logic level ................................ ................................ ................................ ........................... 38 9.6 input ac logic level ................................ ................................ ................................ ........................... 38 9.7 capacitance ................................ ................................ ................................ ................................ ........ 39 9.8 leakage and output buffer characteristics ................................ ................................ ........................ 39 9.9 dc characteristics ................................ ................................ ................................ .............................. 40 9.10 idd measurement test parameters ................................ ................................ ................................ .... 42 9.11 ac characteristics ................................ ................................ ................................ .............................. 43 9.11.1 a c characteristics and operating condition for - 18 speed grade ................................ ... 43 9.11.2 ac characteristics and operating condition for - 25/25i/ - 3 speed grades ........................ 45 9.12 ac input test conditions ................................ ................................ ................................ .................... 66 9.13 differential input/output ac logic levels ................................ ................................ ........................... 66 9.14 ac overshoot / undershoot specification ................................ ................................ ........................... 67 9.14.1 ac overshoot / undershoot specification for address and control pins: ........................ 67 9.14.2 ac overshoot / undershoot specification for clock, data, strobe and mask pins: .......... 67 10. timing waveforms ................................ ................................ ................................ ....................... 68 10.1 command input timing ................................ ................................ ................................ ....................... 68 10.2 odt timing for active/standby mode ................................ ................................ ................................ . 69 10.3 odt timing for power down mode ................................ ................................ ................................ .... 69 10.4 odt timing mode switch at entering power down mode ................................ ................................ .... 70 10.5 odt timing mode switch at exiting power down mode ................................ ................................ ...... 71 10.6 data output (read) timing ................................ ................................ ................................ .................... 72 10 .7 burst read operation: rl=5 (al=2, cl=3, bl=4) ................................ ................................ ................ 72 10.8 data input (write) timing ................................ ................................ ................................ ...................... 73 10.9 burst write operation: rl=5 (al=2, cl=3, wl=4, bl=4) ................................ ................................ .... 73 10.10 seamless burst read operation: rl = 5 (al = 2, and cl = 3, bl = 4) ................................ ....... 74 10.11 seamless burst write operation: rl = 5 (wl = 4, bl = 4) ................................ .......................... 74 10.12 burst read interrupt timing: rl =3 (cl=3, al=0, bl=8) ................................ ............................. 75
W9751G8KB publication release date: feb. 15, 2012 - 3 - revision a01 10.13 burst write interrupt timing: rl=3 (cl=3, al=0, wl=2, bl=8) ................................ .................. 75 10.14 write operation with data mask: wl=3, al=0, bl=4) ................................ ............................... 76 10.15 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=4, trtp 2clks) ............ 77 10.16 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=8, trtp 2clks) ............ 77 10.17 burst read operation followed by precharge: rl=5 (al=2, cl=3, bl=4, trtp 2clks) ............ 78 10.18 burst read operati on followed by precharge: rl=6 (al=2, cl=4, bl=4, trtp 2clks) ............ 78 10.19 burst read operation followed by precharge: rl=4 (al=0, cl=4, bl=8, trtp > 2clks) ............ 79 10.20 burst write operation followed by precharge: wl = (rl - 1) = 3 ................................ .................. 79 10.21 burst write operation followed by precharge: wl = (rl - 1) = 4 ................................ .................. 80 10.22 burst read operation with auto - precharge: rl=4 (al=1, cl=3, bl =8, trtp 2clks) ............... 80 10.23 burst read operation with auto - precharge: rl=4 (al=1, cl=3, bl=4, trtp > 2clks) ............... 81 10.24 burst read with auto - precharge followed by an activation to the same bank (trc limit): rl=5 (al=2, cl=3, internal trcd=3, bl=4, trtp 2clks) ................................ ................................ ....................... 81 10.25 burst read with auto - precharge followed by an activation to the same bank (trp limit): rl=5 (al=2, cl= 3, internal trcd=3, bl=4, trtp 2clks) ................................ ................................ ....................... 82 10.26 burst write with auto - precharge (trc limit): wl=2, wr=2, bl=4, trp=3 ................................ . 82 10.27 burst write with auto - precharge (wr + trp limit): wl=4, wr=2, bl=4, trp=3 ....................... 83 10.28 self refresh timing ................................ ................................ ................................ ................... 83 10.29 active power down mode entry and exit timing ................................ ................................ ....... 84 10.30 precharged power down mode entry and exit timing ................................ .............................. 84 10.31 clock frequency change in precharge power down mode ................................ ........................ 85 11. package specification ................................ ................................ ................................ .............. 86 packag e outline wbga60 (8x12.5 mm 2 ) ................................ ................................ ................................ ........ 86 12. revision history ................................ ................................ ................................ .......................... 87
W9751G8KB publication release date: feb. 15, 2012 - 4 - revision a01 1. general description the W9751G8KB is a 512 m b its ddr2 s dram , organized as 16 , 777 , 216 words ? 4 banks ? 8 bits. this device achieves high speed transfer rates up to 1066mb/sec/pin (ddr2 - 1066) for general applications. W9751G8KB is sorted into the following speed grades: - 18 , - 25 , 25i and - 3 . the - 18 is compliant to the ddr2 - 1066 (7 - 7 - 7) specification . t he - 25 /25i are compliant to the ddr2 - 800 (5 - 5 - 5) or ddr2 - 800 (6 - 6 - 6) specification ( the 25 i industrial grade which is guaranteed to support - 4 0 c t case 9 5 c ) . t he - 3 is compliant to the ddr2 - 667 (5 - 5 - 5) specification . all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the cross point of diffe rential clocks (clk rising and falling). all i/os are synchronized with a single ended dqs or differential dqs - pair in a source synchronous fashion. 2. features ? power supply: v dd , v ddq = 1.8 v ? 0.1 v ? doub le data rate architecture: two data transfers per clock cycle ? cas latency: 3, 4 , 5, 6 and 7 ? burst length: 4 and 8 ? bi - directional, differential data strobes (dqs and ) are transmitted / received with data ? edge - aligned with r ead data and center - aligned with w rite data ? dll aligns dq and dqs transitions with clock ? differential clock inputs (c l k and ) ? data masks (dm) for write data . ? commands entered on each positive c l k edge , data and data mask are referenced to bo th edges of dqs ? posted programmable additive latency supported to make command and data bus efficiency ? read latency = additive latency plus cas latency (rl = al + cl) ? off - chip - driver impedance adjustment (ocd) and on - die - termination (odt) for better signal quality ? auto - precharge operation for read and write bursts ? auto r efresh and s elf r efresh modes ? precharged power down and active power down ? write data mask ? write latency = read latency - 1 ( w l = r l - 1 ) ? interface: sstl_1 8 ? packaged in w bga 60 ball ( 8 x1 2.5 mm 2 ) , using lead free materials with rohs compliant cas clk dqs
W9751G8KB publication release date: feb. 15, 2012 - 5 - revision a01 3. key parameters s ym. speed grade ddr2 - 1066 ddr2 - 800 ddr2 - 667 bin(cl - trcd - trp) 7 - 7 - 7 5 - 5 - 5/6 - 6 - 6 5 - 5 - 5 part number extension - 18 - 25/25i - 3 t c k ( avg ) average clock period @ cl = 7 min. 1.875 ns ? ? m ax . 7.5 ns ? ? @ cl = 6 min. 2. 5 ns 2.5 ns ? m ax . 7.5 ns 8 ns ? @ cl = 5 min. 3 ns 2.5 ns 3 ns m ax . 7.5 ns 8 ns 8 ns @ cl = 4 min. 3.75 ns 3.75 ns 3.75 ns m ax . 7.5 ns 8 ns 8 ns @ cl = 3 min. ? 5 ns 5 ns m ax . ? 8 ns 8 ns t r cd active to read/write command delay time min. 13.125 ns 1 2. 5 ns 15 ns t r p precharge to active command period min. 13.125 ns 1 2. 5 ns 15 ns t rc active to ref/active command period min. 5 8 .125 ns 5 7 .5 ns 60 ns t ras active to precharge command period min. 4 5 ns 4 5 ns 4 5 ns i dd 0 operating current max. 6 5 ma 55 ma 5 5 ma i dd1 operation c urrent (single bank) max. 70 ma 62 ma 60 ma i dd4 r operating burst read current max. 1 2 0 ma 85 ma 8 0 ma i dd4 w operating burst write current max. 1 2 5 ma 11 0 ma 105 ma i dd 5b burst r efresh c urrent max. 85 ma 8 0 ma 8 0 ma i dd 6 self refresh current ( t case 85 c ) max. 6 ma 6 ma 6 ma i dd 7 operating b ank i nterleave r ead c urrent max. 135 ma 12 0 ma 1 1 0 ma
W9751G8KB publication release date: feb. 15, 2012 - 6 - revision a01 4. ball configuration 1 2 3 4 5 6 7 8 9 a b c d e f g h j k l d q s v d d q c a s a 2 a 6 v s s q d q 0 c l k a 0 a 4 c l k c s d q 7 v d d o d t n c v d d l a 3 c k e b a 0 b a 1 w e d q 3 d m / r d q s v s s v d d d q 6 v d d q d q 4 v s s v d d a 1 2 n c a 1 3 n c a 1 1 a 8 a 9 a 7 a 5 a 1 a 1 0 / a p v s s v r e f d q 1 v s s q v d d q v s s q n u / r d q s v s s q d q s v d d q v d d q d q 5 v d d v s s v s s q d q 2 v s s d l r a s
W9751G8KB publication release date: feb. 15, 2012 - 7 - revision a01 5. ball description ball number symbol function description h8,h3,h7,j2,j8,j3, j7,k2,k8,k3,h2,k7, l2 ,l8 a0 ? a1 3 address provide the row address for active commands, and the column address and auto - precharge bit for r ead /w rite commands to select one location out of the memory array in the respective bank. row address: a0?a1 3 . column address: a0? a 9 . (a10 is used for auto - precharge) g 2, g 3 ba0 ? ba 1 bank select ba0 ? ba 1 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or one of the extended mode registers is to be accessed during a mrs or emrs command cycle . c8,c2,d7,d3,d1,d9, b1,b9 dq0 ? dq7 data input / output bi - directional data bus. f 9 odt on die termination control odt (registered high) enables termination resistance internal to the ddr2 sdram. b7,a8 dqs, data strobe / d ifferential read data strobe output with read data, input with write data for source synchronous operation. edge - aligned with read data, center - aligned with write data. is only used when differential data strobe mode is enabled via the control bit at emr (1) [a1 0 ] = 0 . g 8 chip select all commands are masked when is registered high . provides for external r ank selection on systems with multiple r anks. is considered part of the command code. f7,g7,f3 , , command inputs , and (along with ) define the command being entered. b 3 dm /rdqs input data mask / read data strobe dm is an input mask signal for write data. input d ata is masked when dm is sampled high coincident with that input data during a w rite access. dm is sampled on both edges of dqs. although dm is input only, t he dm loading matches the dq and dqs loading. when rdqs is enabled, rdqs is output with read data only a nd is ignored during write data . rdqs is enabled by emr (1) [a11] = 1 . if rdqs is enabled , the dm function is disabled . a2 nu/ not use/d ifferential read data strobe is only used when rdqs is enabled and differential data strobe mode is enabled. i f differential data strobe mode is dis abled via the control bit at emr (1) [a1 0 ] = 1, then ball a2 and a8 are not used. e 8, f 8 clk, differential clock inputs c l k and a re differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of c l k and negative edge of . output (read) data is referenced to the crossings of c l k and (both directions of crossing). f 2 cke clock enable cke (registered high) activates and cke (registered low) deactivates clocking circuitry on the ddr2 sdram. e 2 v ref reference voltage v ref is reference voltage for inputs . a1 ,e9,h9,l1 v dd power supply power supply: 1.8v 0.1v . a3,e3,j 1 , k 9 v ss ground ground . a9,c1,c3,c7,c9 v ddq dq power supply dq power supply: 1.8v 0.1v . a7,b2,b8,d2,d8 v ssq dq ground dq ground. isolated on the device for improved noise immunity. g1, l3, l7 nc no connection no connection . e 1 v ddl dll power supply dll power supply: 1.8v 0.1v . e 7 v ssdl dll ground dll ground . cs ras we rdqs clk cas dqs
W9751G8KB publication release date: feb. 15, 2012 - 8 - revision a01 6. block diagram c k e a 1 0 d l l c l o c k b u f f e r c o m m a n d d e c o d e r a d d r e s s b u f f e r r e f r e s h c o u n t e r c o l u m n c o u n t e r c o n t r o l s i g n a l g e n e r a t o r m o d e r e g i s t e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 2 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 0 c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 3 d a t a c o n t r o l c i r c u i t d q b u f f e r c o l u m n d e c o d e r s e n s e a m p l i f i e r c e l l a r r a y b a n k # 1 n o t e : t h e c e l l a r r a y c o n f i g u r a t i o n i s 1 6 3 8 4 * 1 0 2 4 * 8 r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r r o w d e c o d e r a 0 a 9 a 1 1 a 1 2 a 1 3 b a 0 b a 1 c s r a s c a s w e c l k c l k p r e f e t c h r e g i s t e r o d t c o n t r o l d q 0 | d q 7 d q s d q s r d q s r d q s d m o d t
W9751G8KB publication release date: feb. 15, 2012 - 9 - revision a01 7. functional descripti on 7.1 power - u p and i nitialization s equence ddr2 sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. the follo wing sequence is required for power - up and initialization . 1. apply power and attempt to maintain cke below 0.2 v ddq and odt *1 at a low state (all other inputs may be undefined.) either one of the following sequence is required for power - up. a. the v dd voltage ramp time must be no greater than 200 m s from when v dd ramps from 300 mv to v dd min; and during the v dd voltage ramp, | v dd - v ddq | 0.3 volts. ? v dd , v ddl and v ddq are driven from a single power converter output ? v tt is limited to 0.95 v max ? v ref * 2 tracks v ddq /2 ? v ddq v ref must be met at all times b. voltage levels at i/os and outputs must be less than v ddq during voltage ramp time to avoid dram latch - up. during the ramping of the supply voltages, v dd v ddl v ddq must be maintained and is applicable to both ac and dc levels until the ramping of the supply voltages is complete . ? apply v dd /v ddl * 3 before or at the same time as v dd q ? apply v ddq * 4 before or at the same time as v tt ? v ref * 2 tracks v ddq /2 ? v ddq v ref must be met at all times . 2. start clock and maintain stable condition for 200 s (min.) . 3. after stable power and clock ( c l k , ), apply nop or deselect and take cke high . 4. wait minimum of 400 n s then issue precharge all command. nop or deselect applied during 400 n s period. 5. issue an emrs command to emr (2). (to issue emrs command to emr (2), provide low to ba0, high to ba1 . ) 6. issue an emrs command to emr (3). (to issue emrs command to emr (3), provide high to ba0 and ba1 . ) 7. issue an emrs command to emr ( 1 ) to enable dll. (to is sue dll enable command, provide low to a0, high to ba0 and low to ba1 and a13. and a9=a8=a7=low must be used when issuing this command .) 8. issue a mode register set command for dll reset. ( to issue dll reset command, pr ovide high to a8 and low to ba0 - ba 1 and a13 . ) 9. issue a precharge all command. 10. issue 2 or more auto refresh commands. 11. issue a mrs command with low to a8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) 12. at leas t 200 clocks after step 8 , execute ocd calibration (off chip driver impedance adjustment). if ocd calibration is not used, emrs to emr (1) to set ocd calibration default (a9=a8=a7= high ) followed by emrs to emr (1) to exit ocd calibration mode (a9=a8=a7= low ) must be issued with other operati ng parameters of emr(1). 13. the ddr2 sdram is now ready for normal operation. clk
W9751G8KB publication release date: feb. 15, 2012 - 10 - revision a01 note s : 1. to guarantee odt off, vref must be valid and a low level must be applied to the odt pin. 2. vref must be within 300 mv with respect to vddq/2 during supply ramp time. 3. vdd/vddl voltage ramp time must be no greater than 200 m s from when vdd ramps from 300 mv to vdd min. 4. the vddq voltage ramp time from when vdd min is achieved on vdd to when vddq min is achieved on vddq must be no greater than 500 ms . figure 1 C initialization sequence after power - up 7.2 mode register and extended mode registers operation for application flexibility, burst length, burst type, cas l atency, dll reset function, write recovery time (wr) are user def ined variables and must be programmed with a mode register set (mrs) command. additionally, dll disable function, driver impedance, additive cas l atency, odt (on die termination) , single - ended strobe and ocd (off chip driver impedance adjustment) are also user defined variables and must be programmed with an extended mode register set (emrs) command. contents of the mode register (mr) or extended mode registers emr (1 ) , emr ( 2) and emr ( 3) can be altered by re - executing the mrs or emrs commands. even if the user chooses to modify only a subset of the mr or emr (1 ) , emr ( 2) and emr ( 3) variables, all variables within the addressed register must be redefined when the mrs or emrs commands are issued . mrs, emrs and reset dll do not affect array contents, which m ean re - initialization including those can be executed at any time after power - up without affecting array contents. 7.2.1 mode register set command (mrs) ( = " l " , = " l " , = " l " , = " l " , ba0 = " l " , ba1 = " l " , a0 to a13 = register data) the mode register stores the data for controlling the various operating modes of ddr2 sdram. it programs cas l atency, burst length, burst sequence, test mode, dll reset, write recovery (wr) and v arious vendor specific options to make ddr2 sdram useful for various applications. the default value in the mode register after power - up is not defined, therefore the mode register must be programmed during initialization for proper operation . the ddr2 sdr am should be in all bank precharge state with cke already high prior to writing into the mode register. the mode register set command cycle time (t mrd ) is required to complete the write operation to the mode register. the mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. the mode register is divided into various fields depending on functionality. burst length is defined by a[ 2 : 0 ] with options of 4 and 8 bit burst lengths. the burst length decodes are compatible with ddr sdram. burst address sequence type is defined by a3, cas latency is define d by a[ 6 : 4 ] . the ddr2 cas t ch t cl t is t is 400 ns nop pre all emrs mrs pre all ref mrs ref emrs emrs any cmd t rp t mrd t mrd t rp t rfc t rfc t oit follow ocd flow chart ocd cal . mode exit ocd default min 200 cycle dll reset dll enable clk clk cke command odt t mrd cs ras we
W9751G8KB publication release date: feb. 15, 2012 - 11 - revision a01 does not support half clock latency mode. a7 is used for test mode. a8 is used for dll reset. a7 must be set to low for normal mrs operation. write recovery time wr is defined by a[ 11 : 9 ] . refer to the table for specific codes. note: 1. a13 reserved for future use and must be set to " 0 " when programming the mr . 2. wr (write recovery for auto - precharge) min is determined by tck(avg) max and wr max is determined by tck(avg) min. wr[cycles] = ru{ twr[n s ] / tck(avg)[ n s ] }, where ru stands for round up. the mode register must be programmed to this value. this is also used with trp to determine tdal figure 2 C mode register set (mrs) 7.2.2 extend mode register set command s (emrs) 7.2.2.1 extend mode register set command (1), emr (1 ) ( = " l " , = " l " , = " l " , = " l " , ba0 = " h " , ba1 = " l , a0 to a13 = register data) the extended mode register (1) stores the data for enabling or disabling the dll, output driver strength, additive latency, odt, disable, ocd program. the default value of the extended mode register (1) is not defined, therefore the extended mode register (1) must be programmed during initialization for proper operation. the ddr2 sdram should be in all bank precharge with cke already high prior to writing into the extended mode register (1). the mode register set command cycle time (t mrd ) must be satisfied to complete the write operation to the extended mode register (1). extended mode register (1) contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. a0 is used fo r dll enable or disable. a1 is used for enabling a reduced strength output driver. a[ 5 : 3 ] determines the additive latency, a[9:7] are used for ocd control, a10 is used for disable and a11 is used for rdqs enable . a2 and a6 are us ed for odt setting. cas cs ras we b a 0 a 1 3 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 * 1 p d w r d l l b t c a s l a t e n c y b u r s t l e n g t h t m a 8 0 1 d l l r e s e t n o y e s b a 1 b a 0 0 0 0 1 1 0 1 1 m r s m o d e m r e m r ( 1 ) e m r ( 2 ) e m r ( 3 ) a 1 2 1 0 a c t i v e p o w e r d o w n e x i t t i m e f a s t e x i t ( u s e t x a r d ) s l o w e x i t ( u s e t x a r d s ) b u r s t l e n g t h a d d r e s s f i e l d m o d e r e g i s t e r w r i t e r e c o v e r y f o r a u t o - p r e c h a r g e c a s l a t e n c y a 6 0 0 0 0 1 1 1 1 a 5 0 0 1 1 0 0 1 1 a 4 0 1 0 1 0 1 1 0 l a t e n c y r e s e r v e d 3 4 5 7 6 r e s e r v e d r e s e r v e d a 2 0 0 a 1 1 1 a 0 0 1 b l 4 8 a 1 1 0 0 0 0 1 1 1 1 a 1 0 0 0 1 1 0 0 1 1 a 9 0 1 0 1 0 1 1 0 w r * 2 r e s e r v e d 2 3 4 5 6 8 7 a 7 0 1 m o d e n o r m a l t e s t a 3 0 1 b u r s t t y p e s e q u e n t i a l i n t e r l e a v e 0 d d r 2 - 6 6 7 d d r 2 - 8 0 0 d d r 2 - 1 0 6 6 d d r 2 - 8 0 0 d d r 2 - 1 0 6 6 d d r 2 - 6 6 7 b a 1 0 dqs
W9751G8KB publication release date: feb. 15, 2012 - 12 - revision a01 7.2.2.2 dll enable/disable the dll must be enabled for normal operation. dll enable is required during power - up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when enter ing self refresh operation and is automatically re - enabled and reset upon exit of self refresh operation. any time the dll is enabled (and subsequently reset), 200 clock cycles must occur before a read command can be issued to allow time for the internal clock to be synchronized with the external clock. failing to wait for synchronization to occur may result in a violation of the t ac or t dqsck parameters . note s : 1. a13 reserved for future use and must be set to " 0 " when programming the e mr (1) . 2. optional for ddr2 - 667 , mandatory for ddr2 - 800 and ddr2 - 1066 . 3. when adjust mode is issued, al from previously set value must be applied . 4. after setting to default, ocd calibration mode needs to be exited by setting a9 - a7 to 000. refer to the section 7.2.3 for detailed information . 5. if rdqs is enabled, the dm function is disabled. rdqs is active for reads and don?t care for writes . figure 3 C emr (1 ) ba 1 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 0 * 1 ocd program bt rtt address field extended mode register ( 1 ) ba 1 ba 0 mrs mode 0 0 0 0 1 1 1 1 mrs emr ( 1 ) emr ( 2 ) emr ( 3 ) a 6 a 2 0 0 0 0 1 1 1 1 wr additive latency qoff rdqs dqs rtt d . i . c dll rtt ( nominal ) odt disabled 75 ohm 150 ohm 50 ohm * 2 0 a 0 1 dll enable enable disable ocd calibration program ocd calibration mode exit ; matain setting adjust mode * 3 ocd calibration default * 4 drive ( 1 ) drive ( 0 ) a 9 a 8 a 7 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 driver impedance adjustment a 12 1 0 output buffer enabled qoff output buffer disabled a 10 1 0 dqs enable disable output driver impedance control reduced normal a 1 0 1 a 5 0 0 0 0 1 1 1 1 a 4 0 0 1 1 0 0 1 1 a 3 0 1 0 1 0 1 1 0 latency 0 3 4 resesved 6 1 2 driver strength control driver size 100 % 60 % 5 additive latency ba 0 a 13 0 a 11 1 0 rdqs enable * 5 disable enable a 10 ( dqs enable ) 0 ( enable ) 1 ( disable ) 0 ( enable ) 1 ( disable ) 0 ( disable ) 0 ( disable ) 1 ( enable ) 1 ( enable ) a 11 ( rdqs enable ) strobe function matrix dqs dqs dqs dqs dqs hi - z rdqs / dm rdqs dqs hi - z dqs dqs hi - z hi - z rdqs hi - z dm dm rdqs rdqs d d r 2 - 6 6 7 / 8 0 0 d d r 2 - 1 0 6 6
W9751G8KB publication release date: feb. 15, 2012 - 13 - revision a01 7.2.2.3 extend mode register set command (2), emr ( 2 ) ( = " l " , = " l " , = " l " , = " l " , ba0 = " l " , ba1 = " h " , a0 to a13 = register data) the extended mode register (2) controls refresh related features. the default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be programmed during initialization for proper operation . the ddr2 sdram should be in all bank precharge state with cke already high prior to writing into the extended mode register (2). the mode register set command cycle time (t mrd ) must be satisfied to complete the write op eration to the extended mode register (2). mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state . note s : 1. a 0 - a6, a8 - a13 are reserved for future use and must be set to " 0 " when programming the emr (2) . 2. when dram is operated at 85 c < t case 95 c the extended s elf r efresh rate must be enabled by setting bit a7 to "1" before the s elf r efresh mode can be entered . figure 4 C emr (2 ) cas cs ras we ba 1 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 self address field extended mode register ( 2 ) a 7 1 0 disable high temperature self refresh rate enable enable * 2 ba 0 a 13 1 ba 1 ba 0 mrs mode 0 0 0 0 1 1 1 1 mrs emr ( 1 ) emr ( 2 ) emr ( 3 ) 0 * 1 0 * 1
W9751G8KB publication release date: feb. 15, 2012 - 14 - revision a01 7.2.2.4 extend mode register set command (3), emr (3 ) ( = " l " , = " l " , = " l " , = " l " , ba0 = " h " , ba1 = " h " , a0 to a13 = register data) no function is defined in extended mode register (3). the default value of the emr (3) is not defined, therefore the emr (3) must be programmed during init ialization for proper operation . note: 1. all bits in emr (3) except ba0 and ba1 are reserved for future use and must be set to " 0 " when programming the emr(3) . figure 5 C emr (3 ) cas cs ras we ba 1 ba 0 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 1 address field extended mode register ( 3 ) 0 * 1 a 13
W9751G8KB publication release date: feb. 15, 2012 - 15 - revision a01 7.2.3 off - chip driver (ocd) impedance adjustment ddr2 sdram supports driver calibration feature and the flow chart in figure 6 is an example of the sequence. every calibration mode command should be followed by ocd calibration mode exit before any other command being issued. mrs should be set before entering ocd impedance adjustment and on die termination (odt) should be carefu lly controlled depending on system environment . figure 6 C ocd impedance adjustment flow chart s t a r t a l l o k a l l m r s h o u d b e p r o g r a m m e d b e f o r e e n t e r i n g o c d i m p e d a n c e a d j u s t m e n t a n d o d t s h o u l d b e c a r e f u l l y c o n t r o l l e d d e p e n d i n g o n s y s t e m e n v i r o n m e n t e m r s : d r i v e ( 0 ) d q & d q s l o w ; d q s h i g h e m r s : o c d c a l i b r a t i o n m o d e e x i t t e s t n e e d c a l i b r a t i o n e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : e n t e r a d j u s t m o d e b l = 4 c o d e i n p u t t o a l l d q s i n c , d e c o r n o p e m r s : o c d c a l i b r a t i o n m o d e e x i t a l l o k e m r s : d r i v e ( 1 ) d q & d q s h i g h ; d q s l o w t e s t n e e d c a l i b r a t i o n e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : e n t e r a d j u s t m o d e b l = 4 c o d e i n p u t t o a l l d q s i n c , d e c o r n o p e m r s : o c d c a l i b r a t i o n m o d e e x i t e m r s : o c d c a l i b r a t i o n m o d e e x i t e n d
W9751G8KB publication release date: feb. 15, 2012 - 16 - revision a01 7.2.3.1 extended mode register for ocd i mpedance a djustment ocd impedance adjustment can be done using the following emrs mode. in drive mode all outputs are driven out by ddr2 sdram and drive of rdqs is dependent on emr bit enabling rdqs operation . in drive (1) mode, all dq, dqs (and rdqs) signals are driven high and all signals are driven low. in drive (0) mode , all dq, dqs (and rdqs) signals are driven low and all signals are driven high. in adjust mode, bl = 4 of operation code data must be used. in case of ocd calibration default, output driver characteristics have a nominal impedance value of 18 during nominal temperature and voltage conditions. ocd applies on ly to normal full strength output drive setting defined by emr (1) and if reduced strength is set, ocd default driver characteristics are not applicable. when ocd calibration adjust mode is used, ocd default output driver characteristics are not applicable . after ocd calibration is completed or driver strength is set to default, subsequent emrs commands not intended to adjust ocd characteristics must specify a[9:7] as ?000? in order to maintain the default or calibrated value . table 1 C ocd d rive m ode p rogr am a 9 a 8 a 7 operation 0 0 0 ocd calibration mode exit 0 0 1 driv e ( 1) dq, dqs , (rdqs) high and low 0 1 0 driv e ( 0) dq, dqs , (rdqs) low and high 1 0 0 adjust mode 1 1 1 ocd calibration default 7.2.3.2 o cd i mpedance a djust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4 bit burst code to ddr2 sdram as in table 2 . for this operation, burst length has to be set to bl = 4 via mrs command before activating ocd and controllers must drive the burst code to all dqs at the same time. d t0 in table 2 means all dq bits at bit time 0, d t1 at bit time 1, and so forth. the driver output impedance is adjusted for all ddr2 sdram dqs simultaneously and after ocd calibration, al l dqs and dqs?s of a given ddr2 sdram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. the default setting may be any step wi thin the 16 step range. when adjust mode command is issued, al from previously set value must be applied . table 2 C ocd a djust m ode p rogram 4 bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull - up driver strength pull - down driver strength 0 0 0 0 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved dqs
W9751G8KB publication release date: feb. 15, 2012 - 17 - revision a01 for proper operation of adjust mode, wl = rl - 1 = al + cl - 1 clocks and t ds /t dh should be met as shown in figure 7 . for input data pattern for adjustment, d t0 - d t3 is a fixed order and is not affected by burst type (i.e., sequential or interleave) . figure 7 C ocd a djust mode 7.2.3.3 drive mode drive mode, both driv e ( 1) and driv e ( 0), is used for controllers to measure ddr2 sdram driver impedance. in this mode, all outputs are driven out t oit after enter drive mode command and all output drivers are turned - off t oit after ocd calibration mode exit command as shown in figure 8 . figure 8 C ocd drive mode o c d a d j u s t m o d e o c d c a l i b r a t i o n m o d e e x i t w r w l d q s t d s t d h d t 0 c l k d q s _ i n c m d d q _ i n d m n o p e m r s n o p n o p n o p n o p n o p n o p e m r s c l k d t 1 d t 2 d t 3 e n t e r d r i v e m o d e o c d c a l i b r a t i o n m o d e e x i t e m r s e m r s n o p n o p n o p n o p n o p n o p n o p c l k d q s d q s c m d d q t o i t t o i t d q s h i g h f o r d r i v e ( 1 ) d q s l o w f o r d r i v e ( 0 ) d q s h i g h & d q s l o w f o r d r i v e ( 1 ) , d q s l o w & d q s h i g h f o r d r i v e ( 0 ) c l k h i - z
W9751G8KB publication release date: feb. 15, 2012 - 18 - revision a01 7.2.4 on - die termination (odt) on - die termination (odt) is a new feature on ddr2 components that allows a dram to turn on/off termination resistance for each dq, dqs/ , rdqs/ , and dm signal via the odt control pin. the odt feature is designed to improve signal integrity of the memory channel by allowing the dram controller to independently turn on/off termination resistance f or any or all dram devices. the odt function can be used for all active and standby modes. odt is turned off and not supported in self refresh mode . (example timing waveforms refer to 10. 2 , 10. 3 odt timing for active/standby/power down mode and 10.5 , 10.6 odt timing mode switch at e ntering/exiting power down mode diagram in chapter 10) switch (sw1, sw2, sw3) is enabled by odt pin. selection among sw1, sw2, and sw3 is determined by rtt (nominal) in emr (1). termination in cluded on all dqs, dm, dqs, , rdqs, and pins . figure 9 C functional representation of odt 7.2.5 odt related timings 7.2.5.1 mrs command to odt update delay during normal operation the value of the effective termination resistance can b e changed with an emrs command. the update of the rtt setting is done between t mod ,min and t mod ,max, and cke must remain high for the entire duration of t mod window for proper operation. the timings are shown in the following timing diagram . rdqs dram input buffer input pin v ddq sw 1 rval 3 v ddq v ddq sw 2 sw 3 rval 1 rval 2 rval 1 rval 2 rval 3 sw 1 sw 2 sw 3 v ssq v ssq v ssq dqs
W9751G8KB publication release date: feb. 15, 2012 - 19 - revision a01 figure 10 C odt update delay timing - t mod however, to prevent any impedance glitch on the channel, the following conditions must be met . ? t aofd must be met before issuing the emrs command . ? odt must remain low for the entire duration of t mod window, until t mod ,max is met . now the odt is ready for normal operation with the new setting, and the odt signal may be raised again to turned on the odt. following timing diagram shows the proper rtt update procedure . figure 11 C odt update delay timing - t mod , as measured from outside c m d c l k c l k o d t r t t u p d a t i n g n e w s e t t i n g t i s t m o d , m i n t m o d , m a x t a o f d e m r s n o p n o p n o p n o p n o p o l d s e t t i n g 1 ) e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . 2 ) " s e t t i n g " i n t h i s d i a g r a m i s t h e r e g i s t e r a n d i / o s e t t i n g , n o t w h a t i s m e a s u r e d f r o m o u t s i d e . c l k c l k c m d o d t r t t o l d s e t t i n g n e w s e t t i n g t a o n d t i s t m o d , m a x t a o f d e m r s n o p n o p n o p n o p n o p 1 ) e m r s c o m m a n d d i r e c t e d t o e m r ( 1 ) , w h i c h u p d a t e s t h e i n f o r m a t i o n i n e m r ( 1 ) [ a 6 , a 2 ] , i . e . r t t ( n o m i n a l ) . 2 ) " s e t t i n g " i n t h i s d i a g r a m i s w h a t i s m e a s u r e d f r o m o u t s i d e .
W9751G8KB publication release date: feb. 15, 2012 - 20 - revision a01 7.3 command function 7.3.1 bank activate command ( = " l " , = " l " , = " h " , = " h " , ba0, ba1 = bank , a0 to a13 be row address ) the bank activate command must be applied before any read or write operation can be executed. immediately after the bank active command, the ddr2 sdram can accept a read or write command on the following clock cycle. if a read/write command is issued to a bank that has not satisfied the t rcd min specification, then additive latency must be programmed into the device to delay when the read/write command is internally issued to the device. the additive latency value must be chosen to assure t rcd min is satisfied. additive l atencies of 0, 1, 2, 3, 4, 5 and 6 are supported. once a bank has been activated it must be precharged before another bank activate command can be applied to the same bank. the bank active and precharge times are defined as t ras and t rp , respectively. the minimum time interval between successive bank activate commands to the same bank is determined by the ras cycle time of the device (t rc ). the minimum time interval between bank activate command s is t rrd . figure 12 C bank activate command cycle: t rcd = 3, al = 2, t rp = 3, t rrd = 2, t ccd = 2 7.3.2 read command ( = " l " , = " h " , = " l " , = " h " , ba0, ba1 = bank , a10 = " l " , a0 to a9 = column address) the read command is used to initiate a burst read access to an active row. the value on ba 0, ba 1 inputs selects the bank, and the a0 to a9 address inputs determine the starting column address . the address input a10 determines whether or not auto - precharge is used. if auto - precharge is selected, the row be ing accessed will be precharged at the end of the read burst; if auto - precharge is not selected, the row will remain open for subsequent access es. cas cs ras we t 0 t 1 t 2 t 3 t n t n + 1 t n + 2 t n + 3 b a n k a r o w a d d r . b a n k a c o l . a d d r . b a n k b r o w a d d r . b a n k b c o l . a d d r . b a n k a a d d r . b a n k b a d d r . b a n k a r o w a d d r . c a s - c a s d e l a y t i m e ( t c c d ) t r c d = 1 a d d i t i v e l a t e n c y d e l a y ( a l ) r e a d b e g i n s b a n k a a c t i v a t e b a n k a p o s t c a s r e a d b a n k b a c t i v a t e b a n k b p o s t c a s r e a d b a n k a p r e c h a r g e b a n k b p r e c h a r g e b a n k a a c t i v a t e b a n k a c t i v e ( t r a s ) r a s c y c l e t i m e ( t r c ) b a n k p r e c h a r g e t i m e ( t r p ) c o m m a n d a d d r e s s r a s - r a s d e l a y t i m e ( t r r d ) c l k c l k i n t e r n a l r a s - r a s d e l a y ( t r c d m i n )
W9751G8KB publication release date: feb. 15, 2012 - 21 - revision a01 7.3.3 write command ( = " l " , = " h " , = " l " , = " l " , ba0, ba1 = bank , a10 = " l " , a0 to a9 = column address) the write command is used to initiate a burst write access to an active row. the value on ba0, ba 1 inputs selects the bank, and the a0 to a9 address inputs determine the starting column address . the address input a10 determines whether or not auto - precharge is used. if auto - precharge is selected, the row be ing acc essed will be precharged at the end of the write burst; if auto - precharge is not selected, the row will remain open for subsequent accesses. 7.3.4 burst read with auto - precharge command ( = " l " , = " h " , =" l ", = " h ", ba0 , ba1 = bank , a10 = " h " , a0 to a9 = column address) if a10 is high when a read command is issued, the read with auto - p recharge function is engaged. the ddr2 sdram starts an auto - p recharge operation on the rising edge which is (al + bl/2) cycles later than the read with ap command if t ras( min) and t rtp (min) are satisfied. 7.3.5 burst write with auto - precharge command ( = " l " , = " h " , = " l " , = " l " , ba0, ba1 = bank, a10 = " h " , a0 to a9 = column address) if a10 is high when a write command is issued, the write with auto - p recharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completi on of the burst write plus write recovery time (wr) programmed in the mode register. 7.3.6 precharge all command ( = " l " , = " l " , = " h " , = " l " , ba0, ba1 = don?t care, a10 = " h " , a0 to a 9 and a11 = don?t care) the precharge all command precharge all banks simultaneously. then all banks are switched to the idle state. 7.3.7 self refresh entry command ( = " l " , = " l " , = " l " , = " h " , cke = " l " , ba0, ba1, a0 to a13 = don ? t care ) the self refresh command can be used to retain data, even if the rest of the system is powered down. when in the self refresh mode, the ddr2 sd ram retains data without external clocking. the ddr2 sdram device has a built - in timer to accommodate self refresh operation. odt must be turned off before issuing self refresh command, by either driving odt pin low or using an emrs command. once the comma nd is registered, cke must be held low to keep the device in self refresh mode. the dll is automatically disabled upon entering self refresh and is automatically enabled upon exiting self refresh. when the ddr2 sdram has entered self refresh mode, all of the external signals except cke, are don?t care. the clock is internally disabled during self refresh operation to save power. the user may change the external clock frequency or halt the external clock one clo ck after self refresh entry is registered ; however, the clock must be restarted and stable before the device can exit self refresh operation. cas cs ras we
W9751G8KB publication release date: feb. 15, 2012 - 22 - revision a01 7.3.8 self refresh exit command ( cke = " h " , = " h " or cke = " h " , = " l " , = " h " , = " h " , = " h " , ba0, ba1 , a0 to a13 = don ? t care ) the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refresh exit is registered, a delay of at least t xsnr must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. cke must remain high for the entire self refresh exit period t xsrd for prop er operation except for self refresh re - entry. upon exit from self refresh, the ddr2 sdram can be put back into self refresh mode after waiting at least t xsnr period and issuing one refresh command (refresh period of t rfc ). nop or d eselect commands must be registered on each positive clock edge during the self refresh exit interval t xsnr . odt should be turned off during t xsrd . the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh, the ddr2 sdram requires a minimum of one extra auto refresh command before it is put back into self refresh mode. 7.3.9 refresh command ( = " l " , = " l " , = " l " , = " h " , cke = " h " , ba0, ba1 , a0 to a13 = don?t care) refresh is used during normal operation of the ddr2 sdram. this command is non persistent, so it must be issued each time a refresh is required . the refresh addressing is generated by the internal refresh controller. this makes the address bits don?t care during an auto refresh command. the ddr2 sdram requires auto refresh cycles at an average periodic interval of t refi (max.) . when the refresh cycle has com pleted, all banks of the ddr2 sdram will be in the precharged (idle) state. a delay between the auto refresh command (ref) and the next activate command or subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (t rfc ) . to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of eight refresh commands can be posted to any given ddr2 sdram, meaning that the maximum absolute interva l between any refresh command and the next refresh command is 9 x t refi . figure 13 C refresh command cas cs ras we t 0 t 1 t 2 t 3 c l k / c l k c k e c m d t r p t r f c t r f c n o p n o p n o p a n y r e f r e f p r e c h a r g e " h i g h " t m t n t n + 1
W9751G8KB publication release date: feb. 15, 2012 - 23 - revision a01 7.3.10 no - operation command ( = " l " , = " h " , = " h " , = " h " , cke, ba0, ba1 , a0 to a13 = don?t care ) the no - operation command simply performs no operation (same command as device deselect). 7.3.11 device deselect command ( = " h " , , , , cke, ba0, ba1 , a0 to a13 = don?t care ) the device deselect command disables the command decoder so that the , , and address inputs are ignored. this command is similar to the no - operation command. 7.4 read and w rite access modes the ddr2 sdram provides a fast column access operation. a single read or write command will initiate a serial read or write operation on successive clock cycles. the boundary of the burst cyc le is strictly restricted to specific segments of the page length . the 16 mbit x 8 i/o x 4 bank chip has a page length of 1024 bits (defined by ca 0 to c a 9 ) * . t he page length of 1024 is divided into 256 or 128 uniquely addressable boundary segments depending on bur st length, 256 for 4 bit burst, 128 for 8 bit burst respectively. a 4 - bit or 8 - bit burst operation will occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the device during the read or write com mand ( ca 0 to c a 9 ). the second, third and fourth access will also occur within this group segment . h owever, the burst order is a function of the starting address, and the burst sequence . a new burst access must not interrupt the previous 4 bit burst operati on in case of bl = 4 setting. however, in case of bl = 8 setting, two cases of interrupt by a new burst access are allowed, one reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary respectively. the minimum to delay is defined by t ccd , and is a minimum of 2 clocks for read or write cycles . note: page length is a function of i/o organization and column addressing 16 m bits 8 organization (ca0 to ca 9 ); page length = 1024 bits 7.4.1 posted posted operation is supported to make command and data bus efficient for sustainable bandwidths in ddr2 sdram. in this operation, the ddr2 sdram allows a read or write command to be issued immediately after the bank activate command (or any time during the - - delay time, t rcd , period). the command is held for the time of the additive latency (al) before it is issued inside the device. the read latency (rl) is controlled by the sum of al and the cas l atency (cl). therefore if a user chooses to issue a read/write command before the t rcdmin , then al (greater than 0) must be written into the emr (1). the write latency (wl) is always defined as rl - 1 ( r ead l atency - 1) where r ead l atency is defined as the sum of a dditive l atency plus cas l atency (rl = al + cl). read or write operations using al allow seamless bursts . ( example timing waveforms refer to 10. 1 0 and 10.1 1 seamless burst read / write operation diagram in chapter 10 ) 7.4.1.1 examples of posted operation examples of a read followed by a write to the same bank where al = 2 and where al = 0 are shown in figures 1 4 and 1 5 , respectively. cas cs ras we cas cs
W9751G8KB publication release date: feb. 15, 2012 - 24 - revision a01 [al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4, bl = 4] figure 1 4 C example 1: read followed by a write to the same bank, where al = 2 and cl = 3, rl = (al + cl) = 5, wl = (rl - 1) = 4, bl = 4 al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4] figure 1 5 C example 2: read followed by a write to the same bank, where al = 0 and cl = 3, rl = (al + cl) = 3, wl = (rl - 1) = 2, bl = 4 7.4.2 burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). the parameters that define how the burst mode will operate are burst sequence and burst length. the ddr2 sdram supports 4 bit and 8 bit burst modes only. for 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. the burst length is programmable and defined by mr a[2:0]. the burst type, either sequential or interleaved, is programmable and defined by mr [a3] . seamless burst read or write operations are supported . unlike ddr 1 devices, interruption of a burst read or write s cycle during bl = 4 mode operation is prohibited. howev er in case of bl = 8 mode, interruption of a burst read or write operation is limited to c m d 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 0 - 1 c l k / c l k d q s / d q s d q a l = 2 c l = 3 w l = r l - 1 = 4 t r c d r l = a l + c l = 5 d o u t 0 d i n 0 a c t i v e a - b a n k r e a d a - b a n k w r i t e a - b a n k d i n 1 d i n 2 d i n 3 d o u t 1 d o u t 2 d o u t 3 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 0 - 1 c l = 3 w l = r l - 1 = 2 t r c d r l = a l + c l = 3 a l = 0 c m d c l k / c l k d q d o u t 0 d o u t 1 d o u t 2 d o u t 3 d i n 0 d i n 1 d i n 2 d i n 3 w r i t e a - b a n k r e a d a - b a n k a c t i v e a - b a n k d q s / d q s
W9751G8KB publication release date: feb. 15, 2012 - 25 - revision a01 two cases, reads interrupted by a read, or writes interrupted by a write. ( example timing waveforms refer to 10. 1 2 and 10.1 3 burst read and write interrupt timing diag ram in chapter 10) therefore the burst stop command is not supported on ddr2 sdram devices . table 3 C burst length and sequence burst length starting address (a2 a1 a0) sequential addressing (decimal) interleave addressing (decimal) 4 x 00 0, 1, 2, 3 0, 1, 2, 3 x 01 1, 2, 3, 0 1, 0, 3, 2 x 10 2, 3, 0, 1 2, 3, 0, 1 x 11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 7.4.3 burst read mode operation burst read is initiated with a read command . the address inputs determine the starting column address for the burst. t he delay from the start of the command to when the data from the first cell appears on the outputs is equal to t he value of the r ead l atency (rl). the data strobe output (dqs) is driven low one clock cycle before valid data (dq) is driven onto the data bus. the first bit of the burst is synchronized with the rising edge of the data strobe (dqs). each subsequent data - out appears on the dq pin in phase with the dqs signal in a source synchronou s manner. the rl is equal to an a dditive l atency (al) plus cas l atency (cl). the cl is defined by the mode register set (mrs). the al is defined by the extended mode register emr (1) . ( example timing waveform s refer to 10. 6 and 10. 7 data output (read) timing and burst read operation diagram in chapter 10) 7.4.4 burst write mode operation burst write is initiated with a write command . the address inputs determine the starting column address for the burst. write l atency (wl) is defined by a r ead l atency (rl) minus one and is equal to (al + cl - 1); and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first dqs strobe. a data strobe signal (dqs) should be driven low (preamble) nominally half clock prior to the wl. the first data bit of the burst cycle must be applied to the dq pins at the first rising edge of the dqs following the preamble. the t dqss sp ecification must be satisfied for each positive dqs transition to its associated clock edge during write cycles. the subsequent burst bit data are issued on successive edges of the dqs until the burst length is completed, which is 4 or 8 bit burst. when th e burst has finished, any additional data supplied to the dq pins will be ignored. the dq signal is ignored after the burst write operation is complete. the time from the completion of the burst write to bank precharge is the write recovery time (wr) . ( exa mple timing waveform s refer to 10. 8 and 10. 9 data input (write) timing and burst write operation diagram in chapter 10)
W9751G8KB publication release date: feb. 15, 2012 - 26 - revision a01 7.4.5 write data mask one write data mask (dm) pin for each 8 data bits (dq) wi ll be supported on ddr2 sdram, c onsistent with the implementation on ddr 1 sdram . it has identical timings on write operations as the data bits, and though used in a uni directional manner, is internally loaded identically to data bits to insure matched system timing. dm function is disabled, when rdqs / are enabled by emrs(1) . ( example timing waveform refer to 10.1 4 write operation with data mask diagram in chapter 10) 7.5 burst interrupt read or write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8 under the following conditions: 1. read burst of 8 can only be interrupted by another read command. read burst interruption by write or precharge command is prohibited. 2. write burst of 8 can only be interrupted by another write command. write burst interruption by read or precharge command is prohibited. 3. read burst interrupt must occur exactly two clocks after the previous read command. any other read burst interrupt timings are prohibited. 4. write burst interrupt must occur exactly two clocks after the previous write command. any other write burst interrupt timings are prohibited. 5. read or write burst interruption is allowed to any bank inside the ddr2 sdram. 6. read or write burst with auto - p recharge enabled is not allowed to interrupt . 7. read burst inter ruption is allowed by a read with auto - precharge command. 8. write burst interruption is allowed by a write with auto - precharge command. 9. all command timings are referenced to burst length set in the mode register. they are not referenced to the actual burst. for example below : ? minimum read to precharge timing is al + bl/2 where bl is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt). ? minimum write to precharge timing is wl + bl/ 2 + t wr , where t wr starts with the rising clock after the un - interrupted burst end and not from the end of the actual burst end. ( example timing waveform s refer to 10. 1 2 and 10. 1 3 burst read and write interrupt timing diagram in chapter 10) rdqs
W9751G8KB publication release date: feb. 15, 2012 - 27 - revision a01 7.6 precharge operation the precharge command is used to precharge or close a bank that has been activated. the precharge command can be used to precharge each bank independently or all banks simultaneously. three address bits a10, ba 0 and ba 1 are used to define which bank to precharge when th e command is issued . table 4 C bank s election for p recharge by a ddress b its a10 ba1 ba0 precharge bank(s) low low low bank 0 only low low high bank 1 only low high low bank 2 only low high high bank 3 only high don ? t care don ? t care all banks 7.6.1 burst read operation followed by precharge minimum read to p recharge command spacing to the same bank = al + bl/2 + max( rtp , 2) - 2 clks for the earliest possible precharge, the precharge command may be issued on the rising edge which is additive l atency (al) + bl/2 + max( rtp , 2) - 2 clocks after a read command. a new bank active (command) may be issued to the same bank after the ras precharge time (t rp ). a precharge command cannot be issued until t ras is satisfied. the minimum read to precharge spacing has als o to satisfy a minimum analog time from the rising clock edge that initiates the last 4 - bit prefetch of a read to precharge command. this time is called t rtp (read to precharge). for bl = 4 this is the time from the actual read (al after the read command) to precharge command. for bl = 8 this is the time from al + 2 clocks after the read to the precharge command . ( example timing waveforms refer to 10.1 5 to 10. 19 burst read operation followed by precharge diagram in chapter 10) 7.6.2 burst write operation followed by precharge minimum write to precharge command spacing to the same bank = wl + bl/2 clks + t wr for write cycles, a delay must be satisfied from the completion of the l ast burst write cycle until the precharge command can be issued. thi s delay is known as a write recovery time (t wr ) referenced from the completion of the burst write to the precharge command. no precharge command should be issued prior to the t wr delay . ( example timing waveforms refer to 10. 2 0 to 10.2 1 burst write operation followed by precharge diagram in chapter 10) 7.7 auto - precharge o peration before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the a uto - precharge function. when a read or a write command is given to the ddr2 sdram, the timing accepts one extra address, column address a10, to allow the active bank to automatically begin precharge at the earliest possible moment du ring the burst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write com mand is issued, then the a uto - p recharge function is engaged. during a uto - precharge, a read command will execute as normal with the exception that the active bank will begin to precharge o n the rising edge which is cas l atency (cl) clock cycles before the e nd of the read burst. auto - precharge is also implemented during write commands. the precharge operation engaged by the auto - precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. cas
W9751G8KB publication release date: feb. 15, 2012 - 28 - revision a01 this featur e allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon cas l atency) thus improving system performance for random data access. the lockout circuit internally delays the precharge operation until the array restore operation has been completed (t ras satisfied) so that the a uto - precharge command may be issued with any read or write command. 7.7.1 burst read with a uto - precharge if a10 is high when a read command is issued, the read with auto - p recharge function is engaged. the ddr2 sdram starts an auto - p recharge operation on the rising edge which is (al + bl/2) cycles later from the read with ap command if t ras (min) and t r tp (min) are satisfied. ( example timing waveform refer to 10.2 2 burst read operation with auto - precharge diagram in chapter 10) if t ras (min) is not satisfied at the edge, the start point of auto - p recharge operation will be delayed until t ras (min) is satisfied. if t r tp (min) is not satisfied at the edge, the start point of auto - p recharge operation will be delayed until t r tp (min) is satisfied. in case the internal precharge is pushed out by t rtp , t rp starts at the point where t rtp ends (not at the next rising clock edge after this event) . so for bl = 4 the minimum time from read with auto - p recharge to the next activate command becomes al + ru{ (t rtp + t rp ) / t ck } ( example timing waveform r efer to 10.2 3 burst read operation with auto - precharge diagram in chapter 10 . ) , f or bl = 8 the time from read with auto - p recharge to the next activate command is al + 2 + ru{ (t rtp + t rp ) / t ck }, where ru stands for rounded up to the next integer. in any event internal precharge does not start earlier than two clocks after the last 4 - bit prefetch . a new bank active command may be iss ued to the same bank if the following two conditions are satisfied simultaneously . ? the precharge time (t rp ) has been satisfied from the clock at which the auto - p recharge begins . ? the cycle time (t rc ) from the previous bank activation has been satisfied . ( example timing waveforms refer to 10.2 4 to 10.2 5 burst read with auto - precharge followed by an activation to the same bank (t rc limit) and (t rp limit) diagram in chapter 10) 7.7.2 burst write with a uto - precharge if a10 is high when a write command is issued, the write with auto - precharge function is engaged. the ddr2 sdram automatically begins precharge operation after the completion of the burst write plus write recovery time (wr) programmed in the mode register. th e bank undergoing a uto - precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied . ? the data - in to bank activate delay time (wr + t rp ) has been satisfied . ? the cycle time (t rc ) fro m the previous bank activation has been satisfied . ( example timing waveforms refer to 10.2 6 to 10.2 7 burst write with auto - precharge (t rc limit) and (wr + t rp limit ) diagram in chapter 10) ras
W9751G8KB publication release date: feb. 15, 2012 - 29 - revision a01 table 5 C precharge & a uto - precharge clarification s from command to command minimum delay between from command to to command unit notes read precharge (to same bank as read) al + bl/2 + max(rtp, 2) - 2 clks 1, 2 precharge all al + bl/2 + max(rtp, 2) - 2 clks 1, 2 read w/ap precharge (to same bank as read w/ap) al + bl/2 + max(rtp, 2) - 2 clks 1, 2 precharge all al + bl/2 + max(rtp, 2) - 2 clks 1, 2 write precharge (to same bank as write ) wl + bl/2 + t wr clks 2 precharge all wl + bl/2 + t wr clks 2 write w/ap precharge (to same bank as write w/ap) wl + bl/2 + wr clks 2 precharge all wl + bl/2 + wr clks 2 precharge precharge (to same bank as precharge) 1 clks 2 precharge all 1 clks 2 precharge all precharge 1 clks 2 precharge all 1 clks 2 note s : 1. rtp[cycles] = ru{ trtp[n s ] / tck(avg)[n s ] }, where ru stands for round up . 2. for a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank. the precharge period is satisfied after t rp depending on the la test precharge command issued to that bank . 7.8 refresh operation ddr2 sdram requires a refresh of all rows in any rolling 64 ms interval. the necessary refresh can be generated in one of two ways: by explicit auto refresh commands or by an internally timed self refresh mode. dividing the number of device rows into the rolling 64 ms interval defines the average refresh interval, t refi , which is a guideline to controllers for distributed refresh timing . when , and are held low and high at the rising edge of the clock, the chip enters the refresh mode (ref). all banks of the ddr2 sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the refresh command (ref) can be applied. an address counter, internal to the device, supplies the bank address during the refresh cycle. no control of the external address bus is required once this cycle has started . ( example timing waveform refer to 10. 2 8 self refresh diagram in chapter 10) 7.9 power down mode power - down is synchronously entered when cke is registered low, along with nop or deselect command. cke is not allowed to go low while mode register or extended mode register command time, or read or write ope ration is in progress. cke is allowed to go low while any other operation such as row activation, precharge or auto - precharge or auto refresh is in progress, but power down i dd specification will not be applied until finishing those operations. the dll should be in a locked state when power - down is entered. otherwise dll should be reset after exiting power - down mode for proper read operation. cas ras we cs
W9751G8KB publication release date: feb. 15, 2012 - 30 - revision a01 7.9.1 power down entry two types of power down mode can be performed on the device: precharge power down mode and active power down mode . if power down occurs when all banks are idle, this mode is referred to as precharge power down ; if power down occurs when there is a row active in any bank, this mode is referred to as active power down . entering power down deactiva tes the input and output buffers, excluding c l k, , odt and cke. also the dll is disabled upon entering precharge power down or slow exit active power down , but the dll is kept enabled during fast exit active power down . in power down mode, cke low and a stable clock signal must be maintained at the inputs of the ddr2 sdram, and odt should be in a valid state but all other input signals are don?t care. cke low must be maintained until t cke has been satisfied. maximum power down d uration is limited by the refresh requirements of the device, which allows a maximum of 9 x trefi if maximum posting of ref is utilized immediately before entering power down. ( example timing waveforms refer to 10. 29 to 10.3 0 active and precharged power do wn mode entry and exit diagram in chapter 10) 7.9.2 power down exit the power - down state is synchronously exited when cke is registered high (along with a nop or d eselect command). cke high must be maintained until t cke has been satisfied. a valid, executable command can be applied with power - down exit latency, t xp , t xard , or t xards , after cke goes high . power - down exit latency is defined at ac characteristics table of this data sheet . 7.10 input clock frequency change during precharge power down ddr2 sdram input clock frequency can be changed under following condition: ddr2 sdram is in precharged power down mode. odt must be turned off and cke must be at logic low level. a minimum of 2 clocks must be waited after cke goes low before clock frequency may change. sdram input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. during input clock frequency change, odt and cke must be held at stable low l evels. once input clock frequency is changed, stable new clocks must be provided to dram before precharge power down may be exited and dll must be reset via mrs command after precharge power down exit. depending on new clock frequency an additional mrs or emrs command may need to be issued to appropriately set the wr, cl etc during dll re - lock period, odt must remain off. after the dll lock time, the dram is ready to operate with new clock frequency . ( example timing waveform refer to 10.3 1 clock frequency change i n precharge p ower d own mode diagram in chapter 10) clk
W9751G8KB publication release date: feb. 15, 2012 - 31 - revision a01 8. operation mode 8.1 command truth table command cke ba1 ba0 a13 a 12 a11 a10 a9 - a0 notes previous cycle current cycle bank activ ate h h ba row address l l h h 1,2 sin g le bank precharge h h ba x l x l l h l 1,2 precharge all bank s h h x x h x l l h l 1 write h h ba column l column l h l l 1,2, 3 write with auto - precharge h h ba column h column l h l l 1,2, 3 read h h ba column l column l h l h 1,2, 3 read with auto - precharge h h ba column h column l h l h 1,2, 3 ( extended ) mode regis t er set h h ba op code l l l l 1,2 no operation h x x x x x l h h h 1 device deselect h x x x x x h x x x 1 refresh h h x x x x l l l h 1 self refresh entry h l x x x x l l l h 1, 4 self refresh exit l h x x x x h x x x 1,4,5 l h h h power down mode entry h l x x x x h x x x 1,6 l h h h power down mode exit l h x x x x h x x x 1,6 l h h h note s : 1. all ddr2 sdram commands are defined by states of , , , and cke at the rising edge of the clock . 2. bank addresses ba [ 1 : 0] determine which bank is to be operated upon. for (e)mrs ba selects an (extended) mode register . 3. burst reads or writes at bl = 4 can not be terminated or interrupted. see burst interrupt in section 7.5 for details . 4. v r ef must be maintained during self refresh operation . 5. self refresh exit is asynchronous. 6. the power down does not perform any refresh operations. the duration of power down mode is therefore limited by the refresh requi rements outlined in section 7.9 . ras cas cs ras cas we cs we
W9751G8KB publication release date: feb. 15, 2012 - 32 - revision a01 8.2 clock enable (cke) truth table for synchronous transitions current state 2 cke command (n) 3 , , , action (n) 3 notes previous cycle 1 (n - 1) current cycle 1 (n) power down l l x maintain power down 11, 13, 15 l h deselect or nop power down exit 4, 8, 11, 13 self refresh l l x maintain power down 11, 15, 16 l h deselect or nop self refresh exit 4, 5, 9, 16 bank(s) active h l deselect or nop active power down entry 4, 8, 10, 11, 13 all banks idle h l deselect or nop precharge power down entry 4, 8, 10, 11, 13 h l refresh self refresh entry 6, 9, 11, 13 h h refer to the command truth table 7 note s : 1. cke (n) is the logic state of cke at clock edge n; cke (n C 1) was the state of cke at the previous clock edge. 2. current state is the state of the ddr 2 sdram immediately prior to clock edge n. 3. command (n) is the command registered at clock edge n, and action (n) is a result of command (n). 4. all states and sequences not show n are illegal or reserved unless explicitly described elsewhere in this document. 5. on self refresh exit deselect or nop commands must be issued on every clock edge occurring during the t xsnr period. read commands may be issued only after t xsrd (200 clocks) is satisfied. 6. self refresh mode can only be entered from the all banks idle state. 7. must be a legal command as defined in the command truth table. 8. valid commands for power down entry and exit are nop and deselect only. 9. valid commands for self refresh exit are nop and deselect only. 10. power down and self refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. see section 7.9 "power down mode " and section 7.3.7/7.3. 8 " self refresh entry /exit command " for a detailed list of restrictions. 11. t cke min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks o f regist ration. thus, after any cke transition, cke may not transition from its valid level during the time period of t is + 2 x t ck + t ih . 12. the state of odt does not affect the states described in this table. the odt function is not available during self re fresh. see section 7.2.4. 13. the power down does not perform any refresh operations. the duration of power down mode is therefore limited by the refresh requirements outlined in section 7.9 . 14. cke must be maintained high while the sdram is in ocd calibration mode. 15. x means don?t care (including floating around v ref ) in self refresh and power down. however odt must be driven high or low in power down if the odt function is enabled (bit a2 or a6 set to 1 in emr (1) ). 16. v ref must be maintained during self refr esh operation . 8.3 data mask (dm) truth table function dm dqs note write enable l valid 1 write inhibit h x 1 note: 1. used to mask write data, provided coincident with the corresponding data . cs ras cas we
W9751G8KB publication release date: feb. 15, 2012 - 33 - revision a01 8.4 function truth table current state address command action note s idle h x x x x dsl nop or power down l h h h x nop nop or power down l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act row activating l l h l ba, a10 pre/prea precharge / precharge all banks l l l h x aref/self auto refresh or self r efresh 2 l l l l op - code mrs/emrs mode /extended register accessing 2 banks active h x x x x dsl nop l h h h x nop nop l h l h ba, ca, a10 read/reada begin read l h l l ba, ca, a10 writ/writa begin write l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea precharge / precharge all banks l l l h x aref/self illegal l l l l op - code mrs/emrs illegal read h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba , ca, a10 read/reada burst interrupt 1, 3 l h l l ba , ca, a10 writ/writa illegal 1 l l h h ba , ra act illegal 1 l l h l ba , a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa burst interrupt 1, 3 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal cs ras cas we
W9751G8KB publication release date: feb. 15, 2012 - 34 - revision a01 function truth table, continued current state address command action note s read with auto - p recha r ge h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write with auto - precharge h x x x x dsl continue burst to end l h h h x nop continue burst to end l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal precharg e h x x x x dsl nop - > idle after t rp l h h h x nop nop - > idle after t rp l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea nop - > idle after t rp 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal row activating h x x x x dsl nop - > row active after t rcd l h h h x nop nop - > row active after t rcd l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal cs ras cas we
W9751G8KB publication release date: feb. 15, 2012 - 35 - revision a01 function truth table, continued current state address command action note s write recovering h x x x x dsl nop - > b ank active after t wr l h h h x nop nop - > b ank active after t wr l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa new w rite l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal write recovering with auto - precharge h x x x x dsl nop - > p recharge after t wr l h h h x nop nop - > p recharge after t wr l h l h ba, ca, a10 read/reada illegal 1 l h l l ba, ca, a10 writ/writa illegal 1 l l h h ba, ra act illegal 1 l l h l ba, a10 pre/prea illegal 1 l l l h x aref/self illegal l l l l op - code mrs/emrs illegal refreshing h x x x x dsl nop - > idle after t rc l h h h x nop nop - > idle after t rc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal l l l l op - code mrs/emrs illegal mode register accessing h x x x x dsl nop - > idle after t mrd l h h h x nop nop - > idle after t mrd l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/prea illegal l l l h x aref/self illegal l l l l op - code mrs/emrs illegal note s : 1. this command may be issued for other banks, depending on the state of the banks . 2. all banks must be in "idle". 3. read or write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8 . burst read / write can only be interrupted by another re ad / write with 4 bit burst boundary. any other case of read / write interrupt is not allowed. remark: h = high level, l = low level, x = high or low level ( don?t care ), v = valid data. cs ras cas we
W9751G8KB publication release date: feb. 15, 2012 - 36 - revision a01 8.5 s implified s tated d iagram ocd calibration initialization sequence self refreshing refreshing precharge power down activating idle all banks precharged setting mr , emr ( 1 ) emr ( 2 ) emr ( 3 ) active power down bank active reading writing writing with auto - precharge precharging reading with auto - precharge ( e ) mrs ref self ckeh ckel ckeh act pre , prea read ckel ckeh ckel write writa writa reada write reada reada ckel autoomatic sequence command sequence read ckel pre ckel write read ckel pre , prea pre , prea writa ckel = cke low , enter power down ckeh = cke high , exit power down ckeh = cke high , exit self refresh act = activate wr it a = write with auto - precharge r ea da = read ( with auto - precharge pr e a = precharge all ( e ) mrs = ( extended ) mode register set s el f = enter self refresh ref = refresh
W9751G8KB publication release date: feb. 15, 2012 - 37 - revision a01 9. elec t rical characteristics 9.1 a bsolute m aximum r atings parameter symbol rating unit note s voltage on v dd p in relative to v ss v dd - 1.0 ~ 2 .3 v 1, 2 voltage on v ddq p in relative to v ss v dd q - 0.5 ~ 2 .3 v 1, 2 voltage on v ddl p in relative to v ss v ddl - 0.5 ~ 2 .3 v 1, 2 voltage on any p in relative to v ss v in , v out - 0.5 ~ 2 .3 v 1, 2 s torage temperature t stg - 55 ~ 1 0 0 c 1, 2, 3 note s : 1. stresses g r eater than those listed under absolute ma x imum ratings may cause permanent damage to the dev i ce. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . 2. whe n v dd and v ddq and v ddl are less than 500mv; v ref may be equal to or less than 300mv. 3. storage t emperature is the case surface temperature on the center/top side of the dram . 9.2 operating temperature condition parameter symbol rating unit note s operating temperature (for - 18/ - 25/ - 3) t opr 0 ~ 8 5 c 1, 2, 3 operating temperature ( for 25i ) t opr - 40 ~ 9 5 c 1, 2, 3 , 4 note s : 1. operating temperature is the case surface temperature on the center/top side of the dram . 2. supporting 0 ~ 85c with full jedec ac and dc specifications . 3. supporting 0 ~ 85 c and being able to extend to 95 c with doubling a uto r efresh commands in frequency to a 32 m s period ( t refi = 3.9 s ) and to enter to self refresh mode at this high temperature range via a7 " 1" on emr (2). 4. during operation, the dram case temperature must be maintained between - 40 to 95c for industrial parts under all specification parameters . 9.3 r ecommended dc o perating c onditions sym . parameter m in. typ. max. unit note s v dd supply voltage 1.7 1.8 1.9 v 1 v d dl supply voltage for dll 1.7 1.8 1.9 v 5 v ddq supply voltage for output 1.7 1.8 1.9 v 1 , 5 v ref input reference voltage 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v 2, 3 v tt termination voltage (system) v ref - 0.04 v ref v ref + 0.04 v 4 note s : 1. there is no specific device v dd supply voltage requirement for sstl_18 compliance. however under all conditions v ddq must than or equal to v dd . 2. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 3. peak to peak ac noise on v ref may not exceed 2 % v ref (dc) . 4. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and device must track v ref of receiving device . 5. v ddq tracks with v dd , v ddl tracks with v dd . ac parameters are measured with v dd , v ddq and v dddl tied together .
W9751G8KB publication release date: feb. 15, 2012 - 38 - revision a01 9.4 odt dc electrical characteristics parameter /condition sym. min . nom . max . unit note s rtt effective impedance value for emrs(a6,a2)=0,1; 75 rtt1(eff) 60 75 90 1 rtt effective impedance value for emrs(a6,a2)= 1 , 0 ; 150 rtt 2 (eff) 12 0 150 180 1 rtt effective impedance value for emrs(a6,a2)= 1 ,1; 50 rtt 3 (eff) 40 50 60 1, 2 deviation of v m with respect to v ddq /2 v m - 6 +6 % 1 note s : 1. test condition for rtt measurements . 2. optional for ddr2 - 667 , mandatory for ddr2 - 800 and ddr2 - 1066 . measurement definition for rtt(eff) : apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac) ) and i( v il (ac) ) respectively. v ih (ac) , v il (ac) , and v ddq values defined in sstl_18 . rtt(eff) = (v ih(ac) C v il(ac) ) /(i(v ihac) C i(v ilac) ) measurement definition for v m : measure voltage (v m ) at test pin (midpoint) with no load . v m = ((2 x v m / v ddq ) C 1) x 100% 9.5 input dc l ogic l evel parameter sym . min. max. unit dc input logic high v ih(dc) v ref + 0.125 v ddq + 0.3 v dc input logic low v i l (dc) - 0.3 v ref - 0.125 v 9.6 input a c logic level parameter sym. - 18 - 25/25i / - 3 unit min. max. min. max. ac input logic high v ih (ac) v ref + 0.2 00 ? v ref + 0.2 00 v ddq + v peak 1 v ac input logic low v i l (ac) ? v ref - 0.2 00 v ssq - v peak 1 v ref - 0.2 00 v note : 1. refer to the page 6 7 section s 9.14.1 and 9.14.2 ac overshoot/ u ndershoot specification table for v peak value: maximum peak amplitude allowed for o vershoot/ u ndershoo t .
W9751G8KB publication release date: feb. 15, 2012 - 39 - revision a01 9.7 c apacitance sym . parameter min. max. unit c ck input capacitance , clk and 1.0 2.0 pf c dck input capacitance delta , clk and ? 0.25 pf c i input capacitance , all other input - only pins 1.0 2.0 pf c d i i nput capacitance delta, all other input - only pins ? 0.25 pf c io i nput/output capacitance , dq, dm , dqs, ,rdqs, 2.5 3.5 pf c dio i nput/output capacitance delta, dq, dm , dqs, ,rdqs, ? 0.5 pf 9.8 l eakage and o utput b uffer c haracteristics sym . parameter min. max. unit note s i il input leakage current ( 0v v in v dd ) - 2 2 a 1 i ol output leakage current (output disabled, 0v v out v ddq ) - 5 5 a 2 v oh minimum required output pull - up v tt + 0.603 ? v v ol m ax imum required output pull - down ? v tt - 0.603 v v o tr output timing measurement reference level 0.5 x vddq ? v 3 i oh ( dc ) output minimum source dc current - 13.4 ? ma 4 , 6 i ol ( dc ) output minimum sink dc current 13.4 ? ma 5 , 6 note s : 1. a ll other pins not under test = 0 v . 2. dq, dqs, , rdqs, are disabled and odt is turned off . 3. the v ddq of the device under test is referenced. 4. v ddq = 1.7 v; v out = 1.42 v. (v out - v ddq )/i oh must be less than 21 for values of v out between v ddq and v ddq - 0.28 v . 5. v ddq = 1.7 v ; v out = 0.28 v . v out /i ol must be less than 21 for values of v out between 0 v and 0.28 v . 6. the values of i oh (dc) and iol(dc) are based on the conditions given in notes 3 and 4 . they are used to test drive current capability to ensure v ih min plus a noise margin and v il max minus a noise margin are delivered to an sstl_18 receiver . rdqs rdqs clk dqs
W9751G8KB publication release date: feb. 15, 2012 - 40 - revision a01 9.9 dc c haracteristics sym. conditions - 18 - 25/25i - 3 unit note s m ax . m ax . m ax . i dd0 operating current - one b ank active - precharge t ck = t ck (i dd ) , t rc = t rc (i dd ) , t ras = t rasmin (i dd ) ; cke is high, is high between valid commands ; address and control inputs are switching; databus inputs are switching. 6 5 55 5 5 ma 1,2,3,4,5, 6 i dd1 operating current - one b ank active - read - precharge i out = 0 ma ; bl = 4, cl = cl (i dd ) , al = 0; t ck = t ck (i dd ) , t rc = t rc (i dd ) , t ras = t ras min (i dd ) , t rcd = t rcd (i dd ) ; cke is high, is high between valid commands ; address and control inputs are switching; data bus inputs are switching. 70 62 60 ma 1,2,3,4,5, 6 i dd2p precharge power - down current all banks idle; t ck = t ck (i dd ) ; cke is low; other control and address inputs are stable; data bus inputs are floating. ( t case 85 c ) 6 6 6 ma 1,2,3,4,5, 6,7 i dd2n precharge standby current all banks idle; t ck = t ck (i dd ) ; cke is high , is high; other control and address inputs are switching ; data bus inputs are switching. 4 0 35 35 ma 1,2,3,4,5, 6 i dd2q precharge quiet standby current all banks idle; t ck = t ck (i dd ) ; cke is high , is high; other control and address inputs are stable ; data bus inputs are floating. 35 30 30 ma 1,2,3,4,5, 6 i dd3p f active power - down current all banks open; t ck = t ck (i dd ) ; cke is low; other control and address inputs are stable; data bus inputs are floating. ( t case 85 c ) fast pdn exit mrs(12) = 0 10 10 10 ma 1,2,3,4,5, 6 i dd3 ps slow pdn exit mrs(12) = 1 10 10 10 ma 1,2,3,4,5, 6,7 i dd3n active standby current all banks open; t ck = t ck (i dd ) ; t ras = t rasmax (i dd ) , t rp = t rp (i dd ) ; cke is high, is high between valid commands ; other control and address inputs are switching; data b us inputs are switching. 55 45 45 ma 1,2,3,4,5, 6 cs
W9751G8KB publication release date: feb. 15, 2012 - 41 - revision a01 i dd4r operating burst read current all banks open , continuous burst reads , i out = 0 ma; bl = 4, cl = cl (i d d ) , al = 0; t ck = t ck (i dd ) ; t ras = t rasmax (i dd ) , t rp = t rp (i dd ) ; cke is high, is high between valid commands ; address inputs are switching; data bus inputs are switching . 120 85 80 ma 1,2,3,4,5, 6 i dd4w operating burst write current all banks open , continuous burst writes; bl = 4, cl = cl (i d d ) , al = 0; t ck = t ck (i dd ) ; t ras = t rasmax (i dd ) , t rp = t rp (i dd ) ; cke is high, is high between valid commands ; address inputs are switching; data bus inputs are switching. 125 110 105 ma 1,2,3,4,5, 6 i dd5b burst refresh current t ck = t ck (i dd ) ; refresh command every t rfc (i dd ) interval ; cke is high, is high between valid commands ; other control and address inputs are switching ; data bus inputs are switching. 85 80 80 ma 1,2,3,4,5, 6 i dd6 self refresh current cke 0.2 v , external clock off, c l k and at 0 v; other control and address inputs are floating ; data bus inputs are floating. ( t case 85 c ) 6 6 6 ma 1,2,3,4,5, 6,7 i dd7 operating b ank i nterleave r ead c urrent all bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 x t ck (i dd ) ; t ck = t ck (i dd ) , t rc = t rc (i dd ) , t rrd = t rrd (i dd ) , t rcd = t rcd (i dd ) ; cke is h igh, is high between valid commands ; a ddress bus inputs are stable during deselects; data bus inputs are switching . 135 120 110 ma 1,2,3,4,5, 6 note s : 1. v dd = 1.8 v ? 0.1v; v dd q = 1.8 v ? 0. 1 v . 2. i dd specifications are tested after the device is properly initialized . 3. input slew rate is specified by ac parametric test condition. 4. i dd parameter s are specified with odt disabled . 5. data bus consists of dq, dm, dqs, , rdqs, . 6. definitions for i dd low = v in v il (ac) (max) high = v in v ih (ac) (min) stable = inputs stable at a high or low level floating = inputs at v ref = v ddq /2 switching = inputs changing between high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and low every other data transfer (once per clock) for dq signals not including masks or strobes. 7. the following i dd values must be derated (i dd limits increase), when t c ase 85c i dd2p must be derated by 20 %; i dd3p (slow) must be derated by 30 % and i dd6 must be derated by 80 % . (i dd6 will increase by this amount if t c ase < 85c and the 2x refresh option is still enabled) rdqs clk cs dqs
W9751G8KB publication release date: feb. 15, 2012 - 42 - revision a01 9.10 i dd measurement test parameters speed grade ddr2 - 1066 ( - 18) ddr2 - 800 ( - 25/25i ) ddr2 - 667 ( - 3) unit bin( cl - t rcd - t rp ) 7 - 7 - 7 5 - 5 - 5/6 - 6 - 6 5 - 5 - 5 cl ( idd ) 7 5/6 5 tck t ck ( idd ) 1.875 2.5 3 n s t rcd ( idd ) 1 3.125 1 2.5 1 5 n s t rp(idd) 13.125 1 2.5 1 5 n s t rc(idd) 5 8 .125 5 7 .5 60 n s t r asmin (idd) 4 5 4 5 4 5 n s t r asmax (idd) 70000 70000 70000 n s t rrd(idd) - 1kb 7.5 7.5 7.5 n s t faw (idd) - 1kb 35 35 37.5 n s t rfc(idd) 10 5 10 5 10 5 n s
W9751G8KB publication release date: feb. 15, 2012 - 43 - revision a01 9.11 ac c haracteristic s 9.11.1 ac c haracteristics and o perating c ondition for - 18 speed grade notes: 1 - 3 and 45 - 47 apply to the entire table s ym . speed grade ddr2 - 1066 ( - 18) u nit 25 n otes bin( cl - t rcd - t rp ) 7 - 7 - 7 p arameter m in . m ax . t rcd active to read/write command delay time 13.125 ? n s 23 t rp precharge to active command period 13.125 ? n s 23 t rc active to ref/active command period 5 8 .125 ? n s 23 t ras active to precharge command period 4 5 70000 n s 4,23 t rfc auto refresh to active/auto refresh command period 105 ? n s 5 t refi average periodic refresh interval 0 c t cas e 85 c ? 7.8 s 5 85 c < t cas e 9 5 c ? 3.9 s 5,6 t ccd to command delay 2 ? n c k t c k ( avg ) average c lock p eriod t ck ( avg ) @ cl= 4 3.75 7.5 n s 30,31 t ck ( avg ) @ cl= 5 3 7.5 n s 30,31 t ck ( avg ) @ cl= 6 2.5 7.5 n s 30,31 t ck ( avg ) @ cl= 7 1 . 8 75 7.5 n s 30,31 t ch( avg ) average clock high pulse width 0.48 0.52 t c k ( avg ) 30,31 t cl( avg ) average clock low pulse width 0.48 0.52 t c k ( avg ) 30,31 t ac dq output access time from clk/ - 350 350 p s 35 t dqsck dqs output access time from clk / - 325 325 p s 35 t dqsq dqs - dq skew for dqs & associated dq signals ? 175 p s 13 t cke cke minimum high and low pulse width 3 ? n c k 7 t rrd active to active command period for 1kb page size 7.5 ? n s 8,23 t faw four activate window for 1kb page size 35 n s 23 t wr write recovery time 15 ? n s 23 t dal auto - precharge write recovery + precharge time wr + tn rp ? n c k 24 t wtr internal write to read command delay 7.5 ? n s 9,23 t rtp internal read to precharge command delay 7.5 ? n s 4,23 t i s (base) address and control input setup time 125 ? p s 10, 26, 40,42,43 t ih (base) address and control input hold time 200 ? p s 11, 26, 40,42,43 t i s ( ref ) address and control input setup time 325 ? p s 10,26, 40,42,43 t ih ( ref ) address and control input hold time 325 ? p s 11,26, 40,42,43 t i pw address and control input pulse width for each input 0.6 ? t c k ( avg ) t dqss dqs latching rising transitions to associated clock edges - 0.25 0.25 t c k ( avg ) 28 t dss dqs falling edge to clk setup time 0.2 ? t c k ( avg ) 28 t dsh dqs falling edge hold time from clk 0.2 ? t c k ( avg ) 28 t dqsh dqs input high pulse width 0.35 ? t c k ( avg ) t dqsl dqs input low pulse width 0.35 ? t c k ( avg ) clk cas
W9751G8KB publication release date: feb. 15, 2012 - 44 - revision a01 ac c haracteristics and o perating c ondition for - 18 speed grade, continued notes: 1 - 3 and 45 - 47 apply to the entire table s ym . speed grade ddr2 - 1066 ( - 18) u nit s 25 n otes bin( cl - t rcd - t rp ) 7 - 7 - 7 p arameter m in . m ax . t wpre write preamble 0.35 ? c k ( avg ) t wpst write postamble 0.4 0.6 t c k ( avg ) 12 t rpre read preamble 0.9 1.1 t c k ( avg ) 14,36 t rpst read postamble 0.4 0.6 t c k ( avg ) 14,37 t ds(base) dq and dm input setup time 0 ? p s 16,27,29 , 41,42,44 t d h (base) dq and dm input hold time 75 ? p s 17,27,29 , 41,42,44 t ds( ref ) dq and dm input setup time 20 0 ? p s 16,27,29 , 41,42,44 t d h ( ref ) dq and dm input hold time 20 0 ? p s 17,27,29 , 41,42,44 t dipw dq and dm input pulse width for each input 0.35 ? c k ( avg ) t hz data - out high - impedance time from clk/ ? ac ,m ax p s 15,35 t lz(dqs) dqs / - low - impedance time from clk/ t ac ,min t ac ,m ax p s 15,35 t lz(dq) dq low - impedance time from clk/ 2 x t ac ,min t ac ,m ax p s 15,35 t hp clock half p ulse width m in . (t ch(abs) , t cl(abs) ) ? qhs data hold skew factor ? qh dq/dqs output hold time from dqs t hp - t qhs ? xsnr exit self refresh to a non - read command t rfc + 10 ? xsrd exit self refresh to a read command 200 ? c k t xp exit precharge power down to any command 3 ? n c k t xard exit active power down to r ead command 3 ? n c k 1 8 t xards exit active power down to read command (slow exit, lower power) 10 - al ? n c k 1 8,19 t aond odt turn - on delay 2 2 n c k 20 t aon odt turn - on t ac ,min t ac ,m ax + 2.575 n s 20,35 t aonpd odt turn - on (power down mode) t ac ,min + 2 3 x t ck ( avg ) + t ac,max +1 n s t aofd odt turn - off delay 2.5 2.5 n c k 21,39 t ao f odt turn - o ff t ac ,min t ac ,m ax + 0.6 n s 21,38,39 t ao f pd odt turn - o ff (power down mode) t ac ,min + 2 2.5 x t ck ( avg ) + t ac,max + 1 n s t anpd odt to power down e ntry l atency 4 ? c k t a x pd odt power down exit latency 11 n c k t mrd mode r egister s et command cycle time 2 ? c k t m o d mrs command to odt update delay 0 12 n s 23 t oit ocd d rive mode output delay 0 12 n s 23 t delay minimum time clocks remain on after cke asynchronously drops low t is +t ck ( avg ) +t ih ? dqs clk
W9751G8KB publication release date: feb. 15, 2012 - 45 - revision a01 9.11.2 ac c haracteristics and o perating c ondition for - 25/25i / - 3 speed grade s notes: 1 - 3 and 45 - 47 apply to the entire table s ym . speed grade ddr2 - 800 ( - 25/25i ) ddr2 - 667 ( - 3) u nit s 25 n otes bin( cl - t rcd - t rp ) 5 - 5 - 5/6 - 6 - 6 5 - 5 - 5 p arameter m in . m ax . m in . m ax . t rcd active to read/write command delay time 12.5 ? 15 ? n s 23 t rp precharge to active command period 12.5 ? 15 ? n s 23 t rc active to ref/active command period 5 7 .5 ? 60 ? n s 23 t ras active to precharge command period 4 5 70000 4 5 70000 n s 4,23 t rfc auto refresh to active/auto refresh command period 10 5 ? 10 5 ? n s 5 t refi average periodic refresh interval 0 c t cas e 85 c ? 7.8 ? 7.8 s 5 85 c < t cas e 9 5 c ? 3.9 ? 3.9 s 5,6 t ccd to command delay 2 ? 2 ? n c k t c k ( avg ) average c lock p eriod t ck ( avg ) @ cl= 3 5 8 5 8 n s 30,31 t ck ( avg ) @ cl= 4 3.75 8 3.75 8 n s 30,31 t ck ( avg ) @ cl= 5 2.5 8 3 8 n s 30,31 t ck ( avg ) @ cl= 6 2.5 8 ? ? n s 30,31 t ch( avg ) average clock high pulse width 0.48 0.52 0.48 0.52 t c k ( avg ) 30,31 t cl( avg ) average clock low pulse width 0.48 0.52 0.48 0.52 t c k ( avg ) 30,31 t ac dq output access time from clk/ - 400 400 - 450 450 p s 35 t dqsck dqs output access time from clk / - 350 35 0 - 400 40 0 p s 35 t dqsq dqs - dq skew for dqs & associated dq signals ? 2 00 ? 24 0 p s 13 t cke cke minimum high and low pulse width 3 ? 3 ? n c k 7 t rrd active to active command period for 1kb page size 7.5 ? 7.5 ? n s 8,23 t faw four activate window for 1kb page size 35 ? 37.5 ? n s 23 t wr write recovery time 15 ? 15 ? n s 23 t dal auto - precharge write recovery + precharge time wr + tn rp ? wr + tn rp ? n c k 24 t wtr internal write to read command delay 7.5 ? 7.5 ? n s 9,23 t rtp internal read to precharge command delay 7.5 ? 7.5 ? n s 4,23 t i s (base) address and control input setup time 175 ? 200 ? p s 10, 26, 40,42,43 t ih (base) address and control input hold time 2 50 ? 2 75 ? p s 11, 26, 40,42,43 t i s ( ref ) address and control input setup time 375 ? 4 00 ? p s 10,26, 40,42,43 t ih ( ref ) address and control input hold time 375 ? 4 00 ? p s 11,26, 40,42,43 t i pw address and control input pulse width for each input 0.6 ? 0.6 ? t c k ( avg ) t dqss dqs latching rising transitions to associated clock edges - 0.25 0 .25 - 0.25 0 .25 t c k ( avg ) 28 t dss dqs falling edge to clk setup time 0.2 ? 0.2 ? t c k ( avg ) 28 t dsh dqs falling edge hold time from clk 0.2 ? 0.2 ? t c k ( avg ) 28 t dqsh dqs input high pulse width 0.35 ? 0.35 ? t c k ( avg ) t dqsl dqs input low pulse width 0.35 ? 0.35 ? t c k ( avg ) clk cas
W9751G8KB publication release date: feb. 15, 2012 - 46 - revision a01 ac c haracteristics and o perating c ondition for - 25/25i/ - 3 speed grades, continued notes: 1 - 3 and 45 - 47 apply to the entire table s ym . speed grade ddr2 - 800 ( - 25/25i ) ddr2 - 667 ( - 3) u nit s 25 n otes bin( cl - t rcd - t rp ) 5 - 5 - 5/6 - 6 - 6 5 - 5 - 5 p arameter m in . m ax . m in . m ax . t wpre write preamble 0.35 ? ? c k ( avg ) t wpst write postamble 0.4 0.6 0.4 0.6 t c k ( avg ) 12 t rpre read preamble 0.9 1.1 0.9 1.1 t c k ( avg ) 14,36 t rpst read postamble 0.4 0.6 0.4 0.6 t c k ( avg ) 14,37 t ds(base) dq and dm input setup time 5 0 ? 10 0 ? p s 16,27,29 , 41,42,44 t d h (base) dq and dm input hold time 1 25 ? 1 75 ? p s 17,27,29 , 41,42,44 t ds( ref ) dq and dm input setup time 25 0 ? 3 0 0 ? p s 16,27,29 , 41,42,44 t d h ( ref ) dq and dm input hold time 25 0 ? 3 0 0 ? p s 17,27,29 , 41,42,44 t dipw dq and dm input pulse width for each input 0.35 ? ? c k ( avg ) t hz data - out high - impedance time from clk/ ? ac ,m ax ? ac ,m ax p s 15,35 t lz(dqs) dqs / - low - impedance time from clk/ t ac ,min t ac ,m ax t ac ,min t ac ,m ax p s 15,35 t lz(dq) dq low - impedance time from clk/ 2 x t ac ,min t ac ,m ax 2 x t ac ,min t ac ,m ax p s 15,35 t hp clock half p ulse width m in . (t ch(abs) , t cl(abs) ) ? ch(abs) , t cl(abs) ) ? qhs data hold skew factor ? ? qh dq/dqs output hold time from dqs t hp - t qhs ? hp - t qhs ? xsnr exit self refresh to a non - read command t rfc + 10 ? rfc + 10 ? xsrd exit self refresh to a read command 200 ? ? c k t xp exit precharge power down to any command 2 ? 2 ? n c k t xard exit active power down to r ead command 2 ? 2 ? n c k 1 8 t xards exit active power down to read command (slow exit, lower power) 8 - al ? 7 - al ? n c k 1 8,19 t aond odt turn - on delay 2 2 2 2 n c k 20 t aon odt turn - on t ac ,min t ac ,m ax + 0.7 t ac ,min t ac ,m ax + 0.7 n s 20,35 t aonpd odt turn - on (power down mode) t ac ,min + 2 2 x t ck ( avg ) + t ac,max + 1 t ac ,min + 2 2 x t ck ( avg ) + t ac,max + 1 n s t aofd odt turn - off delay 2.5 2.5 2.5 2.5 n c k 21,39 t ao f odt turn - o ff t ac ,min t ac ,m ax + 0.6 t ac ,min t ac ,m ax + 0.6 n s 21,38,39 t ao f pd odt turn - o ff (power down mode) t ac ,min + 2 2.5 x t ck ( avg ) + t ac,max + 1 t ac ,min + 2 2.5 x t ck ( avg ) + t ac,max + 1 n s t anpd odt to power down e ntry l atency 3 ? ? c k t a x pd odt power down exit latency 8 8 n c k t mrd mode r egister s et command cycle time 2 ? ? c k t m o d mrs command to odt update delay 0 12 0 12 n s 23 t oit ocd d rive mode output delay 0 12 0 12 n s 23 t delay minimum time clocks remain on after cke asynchronously drops low t is +t ck ( avg ) + t ih ? is +t ck ( avg ) + t ih ? dqs clk
W9751G8KB publication release date: feb. 15, 2012 - 47 - revision a01 note s : 1. all voltages are referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. odt is disabled for all measurements that are not odt - specific . 3. ac timing reference load : figure 16 C ac timing reference load 4. this is a minimum requirement. minimum read to precharge timing is al + bl / 2 provided that the t rtp and t ras(min) have been satisfied . 5. if refresh timing is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed . 6. this is an optional feature. for detailed information, please refer to operating temperature condition section 9.2 in this data sh eet . 7. t cke min of 3 clocks means cke must be registered on three consecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transition, cke may not transit ion from its valid level during the time period of t is + 2 x t ck + t ih . 8. a minimum of two clocks (2 * n ck ) is required irrespective of operating frequency . 9. t wtr is at least two clocks (2 * n ck ) independent of operation frequency . 10. there are two sets of values listed for c ommand/ address input setup time: tis( base ) and tis( ref ). the tis(ref) value (for reference only) is equivalent to the baseline value of tis(base) at vref w hen the slew rate is 1 .0 v/ns . t he baseline value tis(base) is the jedec defined value, referenced from the input signal crossing at the vih(ac) level for a rising signal and vil(ac) for a falling signal applied to the device under test. see figure 17 . if the c ommand/ a ddress slew rate is not equal to 1 .0 v/ns, then the baseline values must be derated by adding the values from table of tis / tih derating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 (page 5 5 ). figure 17 C differential input wavefo rm timing C t is and t ih d q d q s , d q s r d q s , r d q s o u t p u t t i m i n g r e f e r e n c e p o i n t v t t = v d d q / 2 2 5 v d d q d u t c l k c l k t i s ( b a s e ) t i h ( b a s e ) t i s ( b a s e ) t i h ( b a s e ) v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t i s ( r e f ) t i h ( r e f ) t i s ( r e f ) t i h ( r e f ) l o g i c l e v e l s v r e f l e v e l s
W9751G8KB publication release date: feb. 15, 2012 - 48 - revision a01 11. there are two sets of values listed for c ommand/ address input hold time: tih( base ) and tih( ref ). the tih(ref) value (for reference only) is equivalent to the baseline value of tih(base) at vref w hen the slew rate is 1 .0 v/ns . t he baseline value tih(base) is the jedec defined value, referenced from the input signal crossing at the vil(dc) level for a rising signal and vih(dc) for a falling signal applied to the device under test. see figure 17 . if the c ommand/ a ddress slew rate is no t equal to 1 .0 v/ns, then the baseline values must be derated by adding the values from table tis / tih derating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 (page 5 5 ) . 12. the maximum limit for the t wpst parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) will degrades accordingly . 13. t dqsq : consists of data pin skew and output pattern effects, and p - channel to n - channel variation of the output drivers as well as output slew rate mismatch between dqs / and associated dq in any given cycle . 14. t rpst end point and t rpre begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (t rpst ), or begins driving ( t rpre ). figure 18 shows a method to calculate these points when the device is no longer driving (t rpst ), or begins driving ( trpre ) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent . 15. t hz and t lz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (t hz ), or begins driving (t l z ) . figure 18 shows a method to calculate the point when device is no longer driving (t hz ), or begins driving ( tlz ) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is cons istent. t lz(dq ) refers to t lz of the dq?s and t lz(dqs) refers to tlz of the ( dqs, , rdqs, ) each treated as single - ended signal. figure 18 C method for calculating transitions and endpoints 16. input waveform timing tds with differential data strobe enabled mr[bit10]=0 . there are two sets of values listed for dq and dm input setup time: tds(base) and tds(ref). the tds(ref) value (for reference only) is equivalent to the baseline value tds(base) at vref w hen the slew rate is 2 .0 v/ns, differentially. the baseline value tds(base) is the jedec defined value, referenced from the input signal crossing at the vih(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the vil(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under t est. dqs, signals must be monotonic between v il (dc)max and v ih (dc)min. see figure 19 . if the differential dqs slew rate is not equal to 2 .0 v/ns, then the baseline values must be derated by adding the values from table of ddr2 - 667 , ddr2 - 800 and ddr2 - 1066 tds / tdh derating with differential data strobe (page 60 ) . 17. input waveform timing tdh with differential data strobe enabled mr[bit10]=0 . there are two sets of values listed for dq and dm input hold time: tdh(base) and tdh(ref). the tdh(ref) value (for reference only) is equivalent to the baseline value tdh(base) at vref w hen the slew rate is 2 .0 v/ns, differentially. the baseline value tdh(base) is the jedec defined value, referenced fr om the differential data strobe crosspoint to the input signal crossing at the vih(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the vil(dc) level for a rising signal applied to the device u nder test. dqs, signals must be monotonic between vil(dc)max and vih(dc)min. see figure 19 . if the differential dqs slew rate is not equal to 2 .0 v/ns, then the baseline values must be derated by adding the values from table of dd r2 - 667, ddr2 - 800 and ddr2 - 1066 tds / tdh derating with differential data strobe (page 60 ). dqs rdqs v o h - x m v v t t - 2 x m v v t t - x m v v o h - 2 x m v v o l + 2 x m v v o l + x m v v t t + x m v v t t + 2 x m v t r p s t e n d p o i n t t r p r e b e g i n p o i n t t h z , t r p s t e n d p o i n t = 2 x t 1 - t 2 t l z , t r p r e b e g i n p o i n t = 2 x t 1 - t 2 t h z t 1 t 2 t l z t 1 t 2 dqs
W9751G8KB publication release date: feb. 15, 2012 - 49 - revision a01 figure 19 C differential input waveform timing C t d s and t d h 18. user can choose which active power down exit timing to use via mrs (bit 12). txard is expected to be used for fast active power down exit timing. txards is expected to be used for slow active power down exit timing . 19. al = additive latency . 20. odt turn on time min is when the device leaves high imped ance and odt resistance begins to turn on. odt turn on time max is when the odt resistance is fully on. both are measure from t aond , which is interpreted differently per speed bin . for ddr2 - 667/800 /1066 , taond is 2 clock cycles after the clock edge that registered a first odt high counting the actual input clock edges. 21. odt turn off time min is when the device starts to turn off odt resistance. odt turn off time max is when the bus is in high impedance . both are measured from taofd . for ddr2 - 667/800 : i f tck(avg) = 3 ns is assumed, taofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges . for ddr2 - 1066 : taofd is 0.9375 [ ns ] (= 0.5 x 1.875 [ n s ]) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges . 22. the clock frequency is allowed to change during s elf r efresh mode or precharge power - down mode. in case of c lock frequency change during precharge power - down, a specific procedure is required as described in section 7.10 . 23. for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / tck(avg)}, which is in clock cycles , assuming all input clock jitter specifications are satisfied. e xample s : t he device will support tnrp = ru{trp / tck(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr2 - 667 5 - 5 - 5, of which trp = 15 ns , the device will support tnrp = ru{trp / tck(avg)} = 5, i.e. as long as the input clock jitter specifications are met, precharge command at tm and active command at tm+5 is valid even if (tm+5 - tm) is less than 15 ns due to input clock jitter . for ddr2 - 1066 7 - 7 - 7 , of which trp = 1 3 . 1 25 ns , the device will support tnrp = ru{trp / tck(avg)} = 7 , i.e. as long as the input clock jitter specifications are met, precharge command at tm and active command at tm+ 7 is valid even if (tm+ 7 - tm) is less than 1 3 . 1 2 5 n s d ue to input clock jitter. 24. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [p s ] / tck(avg) [p s ] }, where wr is the value programmed in the mode register set and ru stands for round up . exam ple : for ddr2 - 1066 7 - 7 - 7 at tck(avg) = 1.875 ns with wr programmed to 8 nck, tdal = 8 + ru{1 3 . 1 25 ns / 1.875 ns } [nck] = 8 + 7 [nck] = 1 5 [nck] . d q s d q s t d s ( b a s e ) t d h ( b a s e ) t d s ( b a s e ) t d h ( b a s e ) v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t d s ( r e f ) t d h ( r e f ) t d s ( r e f ) t d h ( r e f ) l o g i c l e v e l s v r e f l e v e l s
W9751G8KB publication release date: feb. 15, 2012 - 50 - revision a01 25. new units, ?tck(avg)? and ?nck?, are introduced in ddr2 - 667 , ddr2 - 800 and ddr2 - 1066. unit ?tck(avg)? represents the actual tck(avg) of the input clock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges. example s : for ddr2 - 667/800 : txp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+2, even if (tm+2 - tm) is 2 x tck(avg) + terr(2per),min. for ddr2 - 1066: txp = 3 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+ 3 , even if (tm+ 3 - tm) is 3 x tck(avg) + terr( 3 per),min. 26. these parameters are measured from a command/address signal (cke, , , , , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (c l k / ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. that is, these parameters should be met whether clock jitter i s present or not. 27. if tds or tdh is violated, data corruption may occur and the data must be re - written with valid data before a valid read can be executed. 28. these parameters are measured from a data strobe signal (dqs , , rdqs, ) crossing to its respective clock signal (c l k/ ) crossing. the spec values are not affected by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 29. these parameters are measured from a data signal (dm, dq0, dq1, etc.) transition edge to its respective data strobe signal (dqs , , rdqs, ) crossing . dqs cs ras we rdqs clk cas
W9751G8KB publication release date: feb. 15, 2012 - 51 - revision a01 30. input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter sp ec parameters'. the jitter specified is a random jitter meeting a gaussian distribution. inpu t clock - jitter s pecifications parameter s for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 parameter symbol ddr2 - 667 ddr2 - 800 ddr2 - 1066 u nit m in . m ax . m in . m ax . m in . m ax . clock period jitter tjit(per) - 125 125 - 100 100 - 90 90 ps clock period jitter during dll locking period tjit(per ,lck ) - 100 100 - 80 80 - 80 80 ps cycle to cycle clock period tjit( cc ) - 250 250 - 200 200 - 180 180 ps cycle to cycle clock period jitter during dll locking period tjit( cc,lck ) - 200 200 - 160 160 - 160 160 ps cumulative error across 2 cycles t err ( 2 per) - 175 175 - 150 150 - 132 132 ps cumulative error across 3 cycles t err ( 3 per) - 225 225 - 175 175 - 157 157 ps cumulative error across 4 cycles t err ( 4 per) - 250 250 - 200 200 - 175 175 ps cumulative error across 5 cycles t err ( 5 per) - 250 250 - 200 200 - 188 188 ps cumulative error across n cycles , n = 6 ... 10, inclusive t err ( 6 - 10 per) - 350 350 - 300 300 - 250 250 ps cumulative error across n cycles , n = 11 ... 5 0, inclusive t err ( 1 1 - 50 per) - 450 450 - 450 450 - 425 425 ps duty cycle jitter tjit( duty ) - 125 125 - 100 100 - 75 75 ps definitions : - tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window. tck ( avg ) = / n where n = 200 - tc h (avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses . tch ( avg ) = / ( n tck ( avg )) where n = 200 tc l (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses . tcl ( avg ) = / ( n tck ( avg )) where n = 200 ? ? ? ? ? ? ? ? n j j tck 1 ? ? ? ? ? ? ? ? n j j tch 1 ? ? ? ? ? ? ? ? n j j tcl 1
W9751G8KB publication release date: feb. 15, 2012 - 52 - revision a01 - tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tcl jitter. tch jitter is the largest deviation of any single t ch from tch(avg). tcl jitter is the largest deviation of any single tcl from tcl(avg) . tjit(duty) = min/max of {tjit(ch), tjit(cl)} where, tjit(ch) = {tchi - tch(avg) where i=1 to 200} tjit(cl) = {tcli - tcl(avg) where i=1 to 200} - tjit(per), tjit(per,lck) tjit(per) is defined as the largest devia tion of any single tck from tck(avg) . tjit(per) = min/max of {tcki - tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not guaranteed through final production testing. - tjit(cc), tjit(cc,lck) tjit(cc) is defined as the difference in clock period between two consecutive clock cycles: tjit(cc) = max of |tcki+1 C tcki| tjit(cc) defines the cycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guaranteed through final production testing. - terr(2per), terr (3per), terr (4per), terr (5per), terr (6 - 10per) and terr (11 - 50per) terr is defined as the cumulative error across multiple consecutive cycles from tck(avg) . t err ( nper ) = C n tck ( avg ) where ? ? ? ? ? ? ? ? ? ? 1 1 n i j j tck ? ? ? ? ? ? ? ? ? ? ? ? ? ? 50per) C r(11 for ter 50 n 11 10per) C r(6 for ter 10 n 6 r(5per) for ter 5 = n r(4per) for ter 4 = n r(3per) for ter 3 = n r(2per) for ter 2 = n
W9751G8KB publication release date: feb. 15, 2012 - 53 - revision a01 31. these parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for calcul ations in the table below.) parameter symbol min max unit absolute clock period tck(abs) tck(avg),min + tjit(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width tc h (abs) tch(avg),min x tck(avg),min + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tc l (abs) tcl(avg),min x tck(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps example s : 1) for ddr2 - 667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 2 ) for ddr2 - 1066, tch(abs),min = ( 0.48 x 1875 ps ) - 75 ps = 825 ps 32. thp is the minimum of the absolute half period of the actual input clock. thp is an input parameter but not an input specification parameter. it is used in conjunction with tqhs to derive th e dram output timing tqh. the value to be used for tqh calculation is determined by the following equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the actual instantaneous clock high time; tcl(abs) is the minimum of the actual instantaneous clock low time; 33. tqhs accounts for: 1) the pulse duration distortion of on - chip clock circuits, which represents how well the actual thp at the input is transferred to the output; and 2) the worst case push - out of dqs on one transition followed by the worst case pull - in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p - channel to n - channel variation of the output drivers 34. tqh = thp C tqhs, where: thp is the minim um of the absolute half period of the actual input clock; and tqhs is the specification value under the max column. {the less half - pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2 - 667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2 - 667 sdram, the dram provides tqh of 1080 ps minimum. 3 ) if the system provides thp of 825 ps into a ddr2 - 106 6 sdram, the dram provides tqh of 575 ps minimum. 4 ) if the system provides thp of 900 ps into a ddr2 - 1066 sdram, the dram provides tqh of 650 ps minimum. 35. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(6 - 10per) of the input clock. (output deratings are relative to the sdram input clock.) examples : 1) i f the measured jitter into a ddr2 - 667 sdram has terr(6 - 10per),min = - 272 ps and terr(6 - 10per),max = + 293 ps , then tdqsck,min(derated) = tdqsck,min - terr(6 - 10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck,max(derated) = tdqsck,max - terr(6 - 10per),min = 400 ps + 272 ps = + 672 ps . similarly, tlz(dq) for ddr2 - 667 derates to tlz(dq),min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz(dq),max(derate d) = 450 ps + 272 ps = + 722 ps . (caution on the min/max usage!) 2) if the measured jitter into a ddr2 - 1066 sdram has terr(6 - 10per),min = - 202 ps and terr(6 - 10per),max = + 223 ps , then tdqsck,min(derated) = tdqsck,min - terr(6 - 10per),max = - 300 ps - 223 ps = - 523 ps and tdqsck,max(derated) = tdqsck,max - terr(6 - 10per),min = 300 ps + 202 ps = + 502 ps. similarly, tlz(dq) for ddr2 - 1066 derates to tlz(dq),min(derated) = - 700 ps - 223 ps = - 923 ps and tlz(dq),max(derated) = 350 ps + 202 ps = + 552 ps . (caution on the min/max usage!)
W9751G8KB publication release date: feb. 15, 2012 - 54 - revision a01 36. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(per) of the input clock. (output deratings are relative to the sdram input clock.) examples : 1) if the measured jitt er into a ddr2 - 667 sdram has tjit(per),min = - 72 ps and tjit(per),max = + 93 ps , then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 2178 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 93 ps = + 2843 ps . (caution on the min/max usage!) 2 ) if the measured jitter into a ddr2 - 1066 sdram has tjit(per),min = - 72 ps and tjit(per),max = + 63 ps , then trpre,min(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 1615.5 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(avg) + 63 ps = + 2125.5 ps . (caution on the min/max usage!) 37. when the device is operated with input clock jitter, this parameter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) e xample s: 1) if the measured jitter into a ddr2 - 667 sdram has tjit(duty),min = - 72 ps and tjit(duty),max = + 93 ps , then trpst,min(derated) = trpst,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 93 ps = + 1592 ps . (caution on the min/max usage!) 2 ) if the measured jitter into a ddr2 - 1066 sdram has tjit(duty),min = - 72 ps and tjit(duty),max = + 63 ps , then trpst,min(derated) = trps t,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 678 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck(avg) + 63 ps = + 1188 ps . (caution on the min/max usage! ) 38. when the device is operated with input clock jitter, this parameter needs t o be derated by { - tjit(duty),max - terr(6 - 10per),max } and { - tjit(duty),min - terr(6 - 10per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) e xample s: 1) if the measured jitter into a ddr2 - 667 sdram has terr(6 - 1 0per),min = - 272 ps , terr(6 - 10per),max = + 293 ps , tjit(duty),min = - 106 ps and tjit(duty),max = + 94 ps , then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6 - 10per),max } = - 450 ps + { - 94 ps - 293 ps } = - 837 ps and taof,max(derated) = tao f,max + { - tjit(duty),min - terr(6 - 10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps . (caution on the min/max usage!) 2 ) if the measured jitter into a ddr2 - 1066 sdram has terr(6 - 10per),min = - 202 ps , terr(6 - 10per),max = + 223 ps , tjit(duty),min = - 66 ps and tjit(duty),max = + 74 ps , then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6 - 10per),max } = - 350 ps + { - 74 ps - 223 ps } = - 647 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6 - 10per),min } = 950 ps + { 66 ps + 202 ps } = + 1218 ps . (caution on the min/max usage!) 39. for taofd of ddr2 - 667/800 /1066 , the 1/2 clock of nck in the 2.5 x nck assumes a tch(avg), average input clock high pulse width of 0.5 relative to tck(avg). taof,min and taof,max shoul d each be derated by the same amount as the actual amount of tch(avg) offset present at the dram input with respect to 0.5. e xample : if an input clock has a worst case tch(avg) of 0.48, the taof,min should be derated by subtracting 0.02 x tck(avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof,max should be derated by adding 0.02 x tck(avg) to it. therefore, we have; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [m ax(0.5, tch(avg),max) - 0.5] x tck(avg) or taof,min(derated) = min(tac,min, tac,min - [0.5 - tch(avg),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measured at the dram input balls. note that these deratings are in addition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6 - 10per). however tac values used in the equations shown above are from the timi ng parameter table and are not der ated. thus the final derated values for taof are; taof,min(derated_final) = taof,min(derated) + { - tjit(duty),max - terr(6 - 10per),max } taof,max(derated_final) = taof,max(derated) + { - tjit(duty),min - terr(6 - 10per),min } 40. timings are specified with command/addre ss input slew rate of 1.0 v/n s . 41. timings are specified with dqs and dm input slew rate of 1.0v/ns . 42. timings are specified with c l k / differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode . clk
W9751G8KB publication release date: feb. 15, 2012 - 55 - revision a01 43. tis and tih (input setup and hold) derating . tis/tih derating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 command/ address slew rate (v/ns) tis and tih derating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 c l k / differential slew rate 2.0 v/ns 1.5 v/ns 1 .0 v/ns u nit tis ti h tis ti h tis ti h 4.0 +150 + 94 +1 8 0 +1 24 + 21 0 +15 4 ps 3.5 +1 43 + 89 +1 73 +1 19 + 203 +1 49 ps 3.0 +1 33 + 83 +1 63 +1 13 +1 93 +1 43 ps 2.5 +1 2 0 + 75 +150 +1 05 +1 8 0 +1 35 ps 2.0 +1 0 0 + 45 +1 3 0 + 75 +1 6 0 +1 05 ps 1.5 + 67 + 21 + 97 + 51 +1 27 + 81 ps 1.0 0 0 + 30 + 30 + 60 + 60 ps 0.9 - 5 - 14 + 25 + 16 + 55 + 46 ps 0.8 - 13 - 31 + 17 - 1 + 47 + 29 ps 0.7 - 22 - 54 + 8 - 24 + 38 + 6 ps 0.6 - 34 - 83 - 4 - 53 +26 - 23 ps 0.5 - 60 - 125 - 30 - 95 0 - 65 ps 0.4 - 100 - 188 - 70 - 158 - 40 - 128 ps 0.3 - 168 - 292 - 138 - 262 - 108 - 232 ps 0.25 - 200 - 375 - 170 - 345 - 140 - 315 ps 0.2 - 325 - 500 - 295 - 470 - 265 - 440 ps 0.15 - 517 - 708 - 487 - 678 - 457 - 648 ps 0.1 - 1000 - 1125 - 970 - 1095 - 940 - 1065 ps for all input signals the total tis (setup time) and tih (hold time) required is calculated by adding the data sheet tis(base) and tih(base) value to the tis and tih derating value respectively. example: tis (tot al setup time) = tis(base) + ti s. setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of v ih (ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref(dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value . s ee figure 20 illustration of nominal slew rate for tis . if the actual signal is later than the nominal slew rate line anywhere between shad ed ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derati ng value . s ee figure 21 illustration of tangent line for tis . hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and the first crossing of vref(dc). hold (tih) nominal slew rate for a fallin g signal is defined as the slew rate between the last crossing of v ih (dc)min and the first crossing of vref(dc). if the actual signal is always later than the nominal slew rate line between shaded ? dc to vref(dc) region?, use nominal slew rate for derating value . s ee figure 22 illustration of nominal slew rate for ti h . if the actual signal is earlier than the nominal slew rate line anywhere between shaded ? dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref (dc) level is used for derating value . s ee figure 23 illustration of tangent line for ti h . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in above tis/tih d erating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 t able , the derating values may obtained by linear interpolation. these values are typically not subject to production test. they are verified by design and characterization. clk
W9751G8KB publication release date: feb. 15, 2012 - 56 - revision a01 figure 20 C illustration of nominal slew rate for t is c l k c l k t i s t i h t i s t i h n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e v r e f t o a c r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r s e t u p s l e w r a t e f a l l i n g s i g n a l = v r e f ( d c ) - v i l ( a c ) m a x s e t u p s l e w r a t e r i s i n g s i g n a l = v i h ( a c ) m i n - v r e f ( d c ) v r e f t o a c r e g i o n t f t r
W9751G8KB publication release date: feb. 15, 2012 - 57 - revision a01 figure 2 1 C illustration of tangent line for t is t i s t i h t i s t i h t a n g e n t l i n e t a n g e n t l i n e v r e f t o a c r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r s e t u p s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] v r e f t o a c r e g i o n n o m i n a l l i n e s e t u p s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v i h ( a c ) m i n - v r e f ( d c ) ] n o m i n a l l i n e c l k c l k t r t f
W9751G8KB publication release date: feb. 15, 2012 - 58 - revision a01 figure 2 2 C illustration of nominal slew rate for t i h t i s t i h t i s t i h n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e d c t o v r e f r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r h o l d s l e w r a t e r i s i n g s i g n a l = v r e f ( d c ) - v i l ( d c ) m a x h o l d s l e w r a t e f a l l i n g s i g n a l = v i h ( d c ) m i n - v r e f ( d c ) d c t o v r e f r e g i o n c l k c l k t r t f
W9751G8KB publication release date: feb. 15, 2012 - 59 - revision a01 figure 2 3 C illustration of tangent line for t i h t i s t i h t i s t i h t a n g e n t l i n e d c t o v r e f r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r d c t o v r e f r e g i o n n o m i n a l l i n e t a n g e n t l i n e n o m i n a l l i n e h o l d s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] h o l d s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v i h ( d c ) m i n - v r e f ( d c ) ] c l k c l k t r t f
W9751G8KB publication release date: feb. 15, 2012 - 60 - revision a01 44. data setup and hold time derating . ddr2 - 667, ddr2 - 800 and ddr2 - 1066 t ds /t dh derating with differential data strobe dq slew rate (v/ns) tds, tdh derating values for ddr2 - 667, ddr2 - 800 and ddr2 - 1066 (all units in ?p s ?; the note applies to the entire table) dqs / differential slew rate 4 .0 v/ns 3 .0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4 v/ns 1.2 v/ns 1 .0 v/ns 0.8 v/ns tds td h tds td h tds td h tds td h tds td h tds td h tds td h tds td h tds td h 2.0 100 45 100 45 100 45 - - - - - - - - - - - - 1.5 67 21 67 21 67 21 79 33 - - - - - - - - - - 1.0 0 0 0 0 0 0 12 12 24 24 - - - - - - - - 0.9 - - - 5 - 14 - 5 - 14 7 - 2 19 10 31 22 - - - - - - 0.8 - - - - - 13 - 31 - 1 - 19 11 - 7 23 5 35 17 - - - - 0.7 - - - - - - - 10 - 42 2 - 30 14 - 18 26 - 6 38 6 - - 0.6 - - - - - - - - - 10 - 59 2 - 47 14 - 35 26 - 23 38 - 11 0.5 - - - - - - - - - - - 24 - 89 - 12 - 77 0 - 65 12 - 53 0.4 - - - - - - - - - - - - - 52 - 140 - 40 - 128 - 28 - 116 for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base ) and tdh(base) value to the tds and tdh derating value respectively. example: tds (total setup time) = tds(base) + tds . setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the f irst crossing of v ih (ac)min. setup (tds) nominal slew rate for a falling signal is defined as the slew rat e between the last crossing of vref(dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rat e line between shaded ?vref(dc) to ac region?, use nominal slew rate for derating value . see figure 24 illustration of nominal slew r ate for tds (differential dqs, ) . if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent lin e to the actual signal from the ac level to dc level is used for derating value . s ee figure 25 illustration of tangent line for tds (differential dqs, ) . hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and th e first crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih (dc)min and the first crossing of vref(dc). if the actual signal is always later than the nomina l slew rate line bet ween shaded ? dc level to vref(dc) region?, use nominal slew rate for derating value . s ee figure 26 illustration of nominal slew rate for td h (differential dqs, ) . if the actual signal is earlier than the nominal slew rate line anyw here between shaded ? dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value . s ee figure 27 illustration of tangent line for td h (differential dqs, ) . although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached vih/il(a c) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac) . for slew rates in between the values listed in above ddr2 - 667, ddr2 - 800 and ddr2 - 1066 tds/tdh derating with differential data strobe t able, the derating values may be obtained by linear interpolation. these values are typically not subject to p roduction test. they are verified by design and characterization . dqs dqs
W9751G8KB publication release date: feb. 15, 2012 - 61 - revision a01 45. slew rate measurement levels : a ) output slew rate for falling and rising edges is measured between vtt - 250 mv and vtt + 250 mv for single ended signals. for differential signals (e.g. dqs - ) output slew rate is measured between dqs - = - 500 mv and dqs - = + 500 mv. output slew rate is guaranteed by design, but is not necessarily tested on each device . b ) i nput slew rate for single ended signals is measured from v ref (dc) to vih(ac),min for rising edges and from v ref (dc) to vil(ac),max for falling edges. for differential signals (e.g. c l k - ) slew rate for rising edges is measured from c l k - = - 250 mv to c l k - = + 500 mv (+ 250 mv to - 500 mv for falling edges) . c ) v id is the magnitude of the difference between the input voltage on c l k and the input voltage on , or between dqs and for differential strobe . 46. ddr2 sdram o utput s lew r ate test load : output slew rate is characterized under the test conditions as shown in below f igure . output s lew rate test load 47. differential data strobe : ddr2 sdram pin timings are specified for either single ended mode or differentia l mode depending on the setting of the emrs enable dqs mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measured is mode dependen t. in single ended mode, timing relationships are measured relative to the rising or falling edges o f dqs crossing at v ref . in differe ntial mode, these timing relationshi ps are measured relative to the cross point of dqs and its compl ement, . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, , must be tied externally to vss thro ugh a 20 to 10 k resistor to insure proper operation . clk d q d q s , d q s r d q s , r d q s o u t p u t t e s t p o i n t v t t = v d d q / 2 2 5 v d d q d u t dqs
W9751G8KB publication release date: feb. 15, 2012 - 62 - revision a01 figure 2 4 C illustration of nominal slew rate for tds (differential dqs, ) t d s t d h t d s t d h n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e v r e f t o a c r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r s e t u p s l e w r a t e f a l l i n g s i g n a l = v r e f ( d c ) - v i l ( a c ) m a x s e t u p s l e w r a t e r i s i n g s i g n a l = v i h ( a c ) m i n - v r e f ( d c ) v r e f t o a c r e g i o n d q s d q s t r t f dqs
W9751G8KB publication release date: feb. 15, 2012 - 63 - revision a01 figure 2 5 C illustration of tangent line for tds (differential dqs, ) d q s d q s t d s t d h t d s t d h t a n g e n t l i n e t a n g e n t l i n e v r e f t o a c r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r s e t u p s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] v r e f t o a c r e g i o n n o m i n a l l i n e s e t u p s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v i h ( a c ) m i n - v r e f ( d c ) ] n o m i n a l l i n e t f t r dqs
W9751G8KB publication release date: feb. 15, 2012 - 64 - revision a01 figure 2 6 C illustration of nominal slew rate for tdh (differential dqs, ) d q s d q s t d s t d h t d s t d h n o m i n a l s l e w r a t e n o m i n a l s l e w r a t e d c t o v r e f r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r h o l d s l e w r a t e r i s i n g s i g n a l = v r e f ( d c ) - v i l ( d c ) m a x h o l d s l e w r a t e f a l l i n g s i g n a l = v i h ( d c ) m i n - v r e f ( d c ) d c t o v r e f r e g i o n t r t f dqs
W9751G8KB publication release date: feb. 15, 2012 - 65 - revision a01 figure 2 7 C illustration tangent line for tdh (differential dqs, ) d q s d q s t d s t d h t d s t d h t a n g e n t l i n e d c t o v r e f r e g i o n v d d q v i h ( a c ) m i n v i h ( d c ) m i n v r e f ( d c ) v i l ( d c ) m a x v i l ( a c ) m a x v s s t f t r d c t o v r e f r e g i o n n o m i n a l l i n e t a n g e n t l i n e n o m i n a l l i n e h o l d s l e w r a t e r i s i n g s i g n a l = t a n g e n t l i n e [ v r e f ( d c ) - v i l ( a c ) m a x ] h o l d s l e w r a t e f a l l i n g s i g n a l = t a n g e n t l i n e [ v i h ( d c ) m i n - v r e f ( d c ) ] t f t r dqs
W9751G8KB publication release date: feb. 15, 2012 - 66 - revision a01 9.12 ac i nput t est c onditions condition symbol value unit note s input reference voltage v ref 0.5 x v ddq v 1 input signal maximum peak to peak swing v swing(max) 1.0 v 1 input signal minimum slew rate slew 1.0 v/n s 2, 3 note s : 1. input waveform timing is referenced to the input signal crossing through the vih/il( ac ) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from vref to vih(ac) min for rising edges and the range f rom vref to vil(ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from vil(ac) to vih(ac) on the positive transitions and vih(ac) to vil(ac) on the negative transitions . 9.13 differential input/output ac logic levels parameter sym. min. max. unit notes ac differential input voltage v id (ac) 0.5 vddq + 0. 6 v 1 ac differential cross point input voltage v ix (ac) 0.5 x vddq - 0.175 0.5 x vddq + 0.175 v 2 ac differential cross point output voltage v o x (ac) 0.5 x vddq - 0.1 2 5 0.5 x vddq + 0.1 2 5 v 3 note s : 1. v id ( ac ) specifies the input differential voltage |vtr - vcp | required for switching, where v tr is the true input signal (such as c l k, dqs) and v cp is the complementary input signal (such as , ). the minimum value is equal to vih ( ac ) - vil ( ac ) . 2. the typical value of v ix ( ac ) is expected to be about 0.5 x v ddq of the transmitting device and vix ( ac ) is expected to track variations in v ddq. v ix ( ac ) indicates the voltage at which differential input signals must cross . 3. the typical value of v ox (ac) is expected to be about 0.5 x v ddq of the transmitting device and v ox (ac) is expec ted to track variation s in vddq . v ox (ac) indicates the voltage at which differential output signals must cross . figure 2 8 C ac input test signal and differential signal level s waveform t f t r v d d q v i h ( a c ) m i n f a l l i n g s l e w = r i s i n g s l e w = v i h ( d c ) m i n v r e f v i l ( d c ) m a x v i l ( a c ) m a x v s s v s w i n g ( m a x ) v r e f - v i l ( a c ) m a x t f v i h ( a c ) m i n - v r e f t r v ddq v ssq v ix or v ox v id v tr crossing point v cp clk dqs
W9751G8KB publication release date: feb. 15, 2012 - 67 - revision a01 9.14 ac overshoot / undershoot specification 9.14.1 ac overshoot / undershoot specification for address and control pins : applies to a0 - a1 3 , ba0 - ba 1 , / cs, / ras, / cas, / we, cke, od t parameter ddr2 - 1066 ddr2 - 800 ddr2 - 667 unit maximum peak amplitude allowed for overshoot area 0. 5 0. 5 0. 5 v maximum peak amplitude allowed for undershoot area 0. 5 0. 5 0. 5 v maximum overshoot area above v dd 0.5 0.66 0.8 v - ns maximum undershoot area below v ss 0.5 0.66 0.8 v - ns 9.14.2 ac overshoot / undershoot specification for clock, data, strobe and mask pin s : applies to dq, dqs , / dqs , rdqs , /rdqs, dm, clk, /cl k parameter ddr2 - 1066 ddr2 - 800 ddr2 - 667 unit maximum peak amplitude allowed for overshoot area 0. 5 0. 5 0. 5 v maximum peak amplitude allowed for undershoot area 0. 5 0. 5 0. 5 v maximum overshoot area above v ddq 0.19 0.23 0.23 v - ns maximum undershoot area below v ssq 0.19 0.23 0.23 v - ns figure 2 9 C ac overshoot and undershoot definition maximum amplitude maximum amplitude overshoot area undershoot area v dd / v ddq volts ( v ) time ( ns ) v ss / v ssq
W9751G8KB publication release date: feb. 15, 2012 - 68 - revision a01 10. timing waveforms 10.1 command input timing clk clk t ck t ck t cl t ch t is t ih t is t ih t is t ih t is t ih t is t ih cs ras cas we a 0 ~ a 1 3 b a 0 , 1 refer to the command truth table
W9751G8KB publication release date: feb. 15, 2012 - 69 - revision a01 10.2 odt timing for active / standby mode 10.3 odt timing for power down mode t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k c k e i n t e r n a l t e r m r e s . t 8 o d t t a o f d t a o n d t i s r t t c l k t i s t i s v i l ( a c ) v i h ( a c ) t 0 t a o n ( m a x ) t a o f ( m i n ) t a o f ( m a x ) t a o n ( m i n ) t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k c k e i n t e r n a l t e r m r e s . t 8 o d t t i s r t t c l k t i s v i l ( a c ) v i h ( a c ) t 0 t a o n p d ( m a x ) t a o f p d ( m i n ) t a o f p d ( m a x ) t a o n p d ( m i n )
W9751G8KB publication release date: feb. 15, 2012 - 70 - revision a01 10.4 odt timing mode switch at entering power down mode c l k t - 5 t 0 c k e r t t t a o n p d ( m a x ) t a o n d t a o f p d ( m a x ) t a o f d t a n p d t i s c l k e n t e r i n g s l o w e x i t a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e t i s t i s t i s t i s t - 4 t - 3 t - 2 t - 1 t 1 t 2 v i l ( a c ) v i l ( a c ) v i h ( a c ) v i h ( a c ) o d t o d t o d t o d t i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d r t t r t t r t t
W9751G8KB publication release date: feb. 15, 2012 - 71 - revision a01 10.5 odt timing mode switch at exiting power down mode c l k t 0 t 7 t 8 t 9 t 1 0 c k e r t t r t t r t t r t t r t t o d t a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d t i s c l k i n t e r n a l t e r m r e s . t a x p d e x i t i n g f r o m s l o w a c t i v e p o w e r d o w n m o d e o r p r e c h a r g e p o w e r d o w n m o d e t 1 t 5 t 6 t i s t i s t i s t i s t a o f d t a o f p d ( m a x ) t a o n p d ( m a x ) t a o n d v i l ( a c ) v i l ( a c ) v i h ( a c ) v i h ( a c ) i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . i n t e r n a l t e r m r e s . o d t o d t o d t a c t i v e & s t a n d b y m o d e t i m i n g s t o b e a p p l i e d p o w e r d o w n m o d e t i m i n g s t o b e a p p l i e d v i h ( a c )
W9751G8KB publication release date: feb. 15, 2012 - 7 2 - revision a01 10.6 data output ( r ead ) timing 10.7 burst r ead operation: rl=5 ( al = 2, cl=3, bl=4) c l k d q s d q t d q s q m a x t d q s q m a x q t q h t r p s t t c l t c h q q q c l k d q s t q h t r p r e d q s d q s n o p n o p n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 8 n o p n o p n o p n o p d o u t a 0 r l = 5 c l = 3 t d q s c k n o p d o u t a 3 d o u t a 1 d o u t a 2 a l = 2 p o s t e d c a s r e a d a n o p n o p n o p n o p n o p n o p n o p n o p
W9751G8KB publication release date: feb. 15, 2012 - 73 - revision a01 10.8 data input ( write ) timing 10.9 burst write operation: rl =5 ( al = 2, cl=3, wl=4, bl= 4 ) v i h ( a c ) v i l ( a c ) d d d d v i h ( d c ) v i l ( d c ) v i h ( d c ) v i l ( d c ) d m i n d m i n d m i n t d s v i h ( a c ) v i l ( a c ) t w p r e t d q s h t d q s l d q s d q s t w p s t t d s t d h t d h d m i n d q s d q d m d q s t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t n d i n a 0 d i n a 1 d i n a 2 d i n a 3 d i n a 0 d i n a 1 d i n a 2 d i n a 3 t d q s s t d q s s t d s s t d s s c o m p l e t i o n o f t h e b u r s t w r i t e n o p n o p n o p n o p n o p n o p n o p p o s t e d c a s w r i t e a t d q s s t d s h t d q s s t w r p r e c h a r g e c l k c m d d q s d q s d q s c a s e 1 : w i t h t d q s s ( m a x ) c a s e 2 : w i t h t d q s s ( m i n ) w l = r l C C d s h d q s c l k d q s d q s t w r
W9751G8KB publication release date: feb. 15, 2012 - 74 - revision a01 10.10 seamless burst read operation: rl = 5 ( al = 2, and cl = 3, bl = 4 ) note: the seamless burst read operation is supported by enabling a read command at every other clock for bl = 4 operation, and every 4 clock for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated . 10.11 seamless burst write operation: rl = 5 ( w l = 4 , bl = 4 ) note: the seamless burst write operation is supported by enabling a write command every other clock for bl = 4 operation, every four clocks for bl = 8 operation. this operation is allowed regardless of same or different banks as long as the banks are activated . t 0 t 1 t 2 t 5 t 3 t 6 t 4 t 7 t 8 p o s t c a s r e a d a p o s t c a s r e a d b n o p n o p n o p n o p n o p n o p n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 c l k c l k c m d d q s d q s d q ' s a l = 2 c l = 3 r l = 5 t 0 t 1 t 2 t 5 t 3 t 6 t 4 t 7 t 8 p o s t c a s w r i t e a p o s t c a s w r i t e b n o p n o p n o p n o p n o p n o p n o p d i n a 0 d i n a 1 d i n a 2 d i n a 3 d i n b 0 d i n b 1 d i n b 2 c l k c l k c m d d q s d q s d q ' s d i n b 3 w l = r l - 1 = 4
W9751G8KB publication release date: feb. 15, 2012 - 75 - revision a01 10.12 burst read interrupt timing : rl =3 (cl=3, al= 0, bl = 8) 10.13 burst write interrupt timing : rl=3 (cl= 3, al =0, wl=2, bl= 8) n o p n o p n o p n o p r e a d a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t b 0 d o u t b 1 d o u t b 2 d o u t b 3 d o u t b 4 d o u t b 5 d o u t b 6 d o u t b 7 r e a d b n o p n o p d q ' s w r i t e a n o p n o p w r i t e b n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 n o p n o p n o p n o p d i n a 0 d i n a 1 d i n a 2 d i n a 3 d i n b 0 d i n b 1 d i n b 2 d i n b 3 d i n b 4 d i n b 5 d i n b 6 d i n b 7 d q ' s
W9751G8KB publication release date: feb. 15, 2012 - 76 - revision a01 10.14 write operation with data mask : wl= 3 , al =0, bl= 4 ) d q s / d q s d q d m v i h ( a c ) v i h ( d c ) t d s t d h t d s t d h w l + t d q s s ( m a x ) t w r w l + t d q s s ( m i n ) w r i t e c l k c m d m a n d d q s / d q s d q d m d q d m c a s e 1 : m i n t d q s s c a s e 2 : m a x t d q s s c l k d q s / d q s v i l ( d c ) v i l ( a c ) v i h ( a c ) v i l ( a c ) v i h ( d c ) v i l ( d c ) d a t a m a s k t i m i n g
W9751G8KB publication release date: feb. 15, 2012 - 77 - revision a01 10.15 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl=4, t rtp 2 clks) 10.16 burst read operation followed by precharge: rl=4 (al=1, cl=3, bl= 8 , t rtp 2 clks ) n o p p r e c h a r g e n o p n o p n o p n o p n o p n o p p o s t c a s r e a d a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t r t p a l + b l / 2 c l k s a l = 1 c l = 3 r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 f i r s t 4 - b i t p r e f e t c h s e c o n d 4 - b i t p r e f e t c h c l k / c l k c m d d q s , d q s d q ' s p r e c h a r g e n o p b a n k a a c t i v a t e n o p n o p n o p p o s t c a s r e a d a n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 t r a s t r t p a l + b l / 2 c l k s t r p a l = 1 c l = 3 r l = 4 n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s
W9751G8KB publication release date: feb. 15, 2012 - 78 - revision a01 10.17 burst read operation followed by precharge: rl= 5 (al= 2 , cl=3, bl= 4 , t rtp 2 clks ) 10.18 burst read operation followed by precharge: rl= 6 (al= 2 , cl= 4 , bl= 4 , t rtp 2 clks ) n o p n o p p r e c h a r g e n o p n o p n o p p o s t c a s r e a d a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t r a s t r t p a l + b l / 2 c l k s t r p a l = 2 c l = 3 r l = 5 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 n o p c l = 3 c l k / c l k c m d d q s , d q s d q ' s d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 n o p n o p n o p p r e c h a r g e n o p n o p n o p p o s t c a s r e a d a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 8 t r a s t r t p a l + b l / 2 c l k s t r p a l = 2 c l = 4 r l = 6 c l = 4
W9751G8KB publication release date: feb. 15, 2012 - 79 - revision a01 10.19 burst read operation followed by precharge: rl= 4 ( al= 0 , cl= 4 , bl= 8 , t rtp > 2 clks ) 10.20 burst write operation followed by precharge: wl = (rl - 1) = 3 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 n o p n o p p r e c h a r g e n o p n o p n o p n o p p o s t c a s r e a d a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 8 d o u t a 5 d o u t a 6 d o u t a 7 d o u t a 4 c l = 4 r l = 4 t r a s t r t p a l + b l / 2 + m a x ( r t p , 2 ) - 2 c l k s t r p f i r s t 4 - b i t p r e f e t c h s e c o n d 4 - b i t p r e f e t c h a l = 0 n o p n o p n o p n o p n o p n o p n o p p o s t c a s w r i t e a p r e c h a r g e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 8 w l = 3 c o m p l e t i o n o f t h e b u r s t w r i t e d i n a 0 d i n a 1 d i n a 2 d i n a 3 t w r
W9751G8KB publication release date: feb. 15, 2012 - 80 - revision a01 10.21 burst write operation followed by precharge: wl = (rl - 1) = 4 10.22 burst read operation with auto - precharge: rl=4 (al=1, cl=3, bl= 8 , t rtp 2 clks ) n o p n o p n o p n o p n o p n o p n o p p o s t e d c a s w r i t e a p r e c h a r g e a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 9 w l = 4 c o m p l e t i o n o f t h e b u r s t w r i t e t w r d i n a 0 d i n a 1 d i n a 2 d i n a 3 n o p n o p n o p b a n k a a c t i v a t e n o p n o p n o p n o p p o s t c a s r e a d a t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s d q ' s t 8 t r t p a l + b l / 2 c l k s t r p a l = 1 c l = 3 r l = 4 d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d o u t a 4 d o u t a 5 d o u t a 6 d o u t a 7 f i r s t 4 - b i t p r e f e t c h s e c o n d 4 - b i t p r e f e t c h t r t p p r e c h a r g e b e g i n s h e r e a 1 0 = 1
W9751G8KB publication release date: feb. 15, 2012 - 81 - revision a01 10.23 burst read operation with auto - precharge: rl=4 (al=1, cl=3, bl=4, t rtp > 2 clks) 10.24 burst read with auto - precharge followed by an activation to the same bank (t rc limit) : rl=5 (al= 2 , cl= 3 , internal t rcd = 3, bl= 4 , t rtp 2 clks ) n o p n o p b a n k a a c t i v a t e n o p n o p n o p p o s t c a s r e a d a n o p t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 t r t p a l + t r t p + t r p a l = 1 c l = 3 r l = 4 n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s 4 - b i t p r e f e t c h p r e c h a r g e b e g i n s h e r e t r p a 1 0 = 1 n o p n o p n o p n o p n o p n o p p o s t c a s r e a d a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 t r a s m i n . ( a l + b l / 2 ) a l = 2 c l = 3 r l = 5 n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a u t o - p r e c h a r g e b e g i n s a 1 0 = 1 t r p t r c m i n .
W9751G8KB publication release date: feb. 15, 2012 - 82 - revision a01 10.25 burst read with auto - precharge followed by an activation to the same bank (t rp limit) : rl=5 (al= 2, cl = 3, internal t rcd =3, bl= 4, t rtp 2 clks ) 10.26 burst write with auto - precharge (t rc limit): wl=2, wr= 2 , bl= 4, t rp = 3 n o p n o p n o p n o p n o p n o p p o s t c a s r e a d a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 c l k / c l k c m d d q s , d q s t 8 t r a s m i n . a l = 2 c l = 3 r l = 5 n o p d o u t a 0 d o u t a 1 d o u t a 2 d o u t a 3 d q ' s a u t o - p r e c h a r g e b e g i n s a 1 0 = 1 t r p m i n . t r c t r c m i n . w l = r l - 1 = 2 w r t r p n o p n o p n o p n o p n o p n o p n o p p o s t c a s w r a b a n k a b a n k a a c t i v a t e t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 a u t o - p r e c h a r g e b e g i n s a 1 0 = 1 c l k / c l k c m d d q s , d q s d q ' s c o m p l e t i o n o f t h e b u r s t w r i t e t m d i n a 0 d i n a 1 d i n a 2 d i n a 3
W9751G8KB publication release date: feb. 15, 2012 - 83 - revision a01 10.27 burs t write with auto - precharge (wr + t rp limit ): wl=4, wr= 2 , bl= 4, t rp = 3 10.28 self refresh timing t r c w l = r l - 1 = 4 w r t r p m i n . n o p n o p n o p n o p n o p n o p n o p p o s t c a s w r a b a n k a b a n k a a c t i v a t e t 0 t 3 t 4 t 5 t 6 t 7 t 8 t 9 c o m p l e t i o n o f t h e b u r s t w r i t e a u t o - p r e c h a r g e b e g i n s a 1 0 = 1 c l k / c l k c m d d q s , d q s t 1 1 d q ' s d i n a 0 d i n a 1 d i n a 2 d i n a 3 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t m t n s e l f r e f r e s h n o p n o n - r e a d c o m m a n d n o p t x s n r t x s r d t i h t i h t i s t i h t i h t i s t i s t r p t i s t a o f d t c k t c h t c l v i l ( a c ) v i h ( a c ) v i l ( a c ) v i h ( a c ) v i l ( d c ) v i h ( d c ) c l k c m d c k e o d t c l k v i l ( a c ) r e a d c o m m a n d
W9751G8KB publication release date: feb. 15, 2012 - 84 - revision a01 10.29 active power down mode entry and exit timing 10.30 precharged power down mode entry and exit timing c l k c l k t 0 t 1 t 2 t n t n + 1 t n + 2 v a l i d c o m m a n d n o p n o p n o p n o p a c t i v a t e t x a r d o r t x a r d s a c t i v e p o w e r d o w n e x i t a c t i v e p o w e r d o w n e n t r y t i s c k e c m d t i s c l k c l k c m d t 0 t 1 t 2 t 3 t n c k e t n + 1 t n + 2 n o p n o p t i s t r p p r e c h a r g e p o w e r d o w n e n t r y p r e c h a r g e p o w e r d o w n e x i t t x p t i s n o p n o p n o p n o p p r e c h a r g e v a l i d c o m m a n d
W9751G8KB publication release date: feb. 15, 2012 - 85 - revision a01 10.31 clock frequency change i n precharge p ower d own mode n o p n o p n o p n o p n o p v a l i d t 0 t 1 t 2 t 4 t x t x + 1 t y t y + 1 t y + 2 t y + 3 t y + 4 t z c l k t i s d l l r e s e t m i n i m u m 2 c l o c k s r e q u i r e d b e f o r e c h a n g i n g f r e q u e n c y s t a b l e n e w c l o c k b e f o r e p o w e r d o w n e x i t f r e q u e n c y c h a n g e o c c u r s h e r e 2 0 0 c l o c k s o d t i s o f f d u r i n g d l l r e s e t c l k c m d c k e o d t t i s t i h t r p t a o f d t x p
W9751G8KB publication release date: feb. 15, 2012 - 86 - revision a01 11. package specificatio n package outline w bga 60 (8x12.5 mm 2 ) 1 6 0 x b a 1 a s e a t i n g p l a n e s y m b o l d i m e n s i o n ( m m ) m i n . n o m . m a x . a a 1 b d e d 1 e 1 e e e d a a a b b b c c c - - - - - - - - - - - - 0 . 1 0 0 . 2 0 - - - - - - 0 . 1 5 0 . 8 0 b s c . 0 . 8 0 b s c . 6 . 4 0 b s c . 8 . 0 0 b s c . 1 . 2 0 0 . 4 0 0 . 5 0 1 2 . 6 0 8 . 1 0 8 . 0 0 1 2 . 5 0 7 . 9 0 1 2 . 4 0 0 . 4 0 0 . 2 5 d e e e 1 e d d 1 2 3 7 8 9 e - - - 0 . 4 5 - - - - - - a b c d e f g h j k l c c c c c a a a a b c b b b p i n a 1 i n d e x p i n a 1 i n d e x s o l d e r b a l l d i a m e t e r r e f e r s . t o p o s t r e f l o w c o n d i t i o n . t h e w i n d o w - s i d e e n c a p s u l a n t b a l l l a n d b a l l o p e n i n g n o t e : 1 . b a l l l a n d : 0 . 5 m m 2 . b a l l o p e n i n g : 0 . 4 m m 3 . p c b b a l l l a n d s u g g e s t e d
W9751G8KB publication release date: feb. 15, 2012 - 87 - revision a01 12. rev i sion history version date page description a01 feb. 15, 2012 all initial formal data sheet important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully in demnify winbond for any damages resulting from such improper use or sales.

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